RU1803909C - Device for arranging in sequence number files - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in the implementation of computer hardware. The aim of the invention is to expand the functionality of the device by arranging several bits. The device contains registers of the beginning and end of a zone, counters of the beginning and end of a zone, a block for preparing addresses for the beginning and end of a zone, a block for generating a bit number for ordering an array of numbers, a memory block for a bit number, comparison elements, multiplexers, groups of AND, OR elements. The device arranges an array of numbers over several successive binary bits. 2 s.p. crystals, 4 ill., 1 tab.

Description

The invention relates to automation and computer engineering,

The aim of the invention is to expand the functionality by arranging an array of numbers in several binary digits.

In FIG. 1 presents a block diagram of the proposed device; in FIG. 2 - Logic | diagram of the operation of the device; in FIG. 3 is a diagram of an array ordering block; in FIG. 4 is a diagram of a single bit,

The device for arranging the array contains the registers of the address of the beginning 1 and the end 2 of the array of numbers, a register 3 of the number M of digits of numbers, a subtracting counter 4 of the digit of the number, a block of hardware stack memory 5 addresses, zones, a block of hardware stack memory 6 bit numbers M registers poi, first 7, second 9 elements of comparison, first 10, second 11, third 12 - registers, first 13, second 14, third 15

- keys, first 16, second 17, third 18 - AND elements, first 19, second 20 - OR elements, first 21, second 22, third 23, fourth 8 - delay elements, first 24, second 25, third 26, fourth 28 fifth 29 - multiplexers, clock input 38, trigger input 39, array sequencer (SD) 40. Registers 10 and 11 are assembled on D-flip-flops. Block 40 contains counters 41 and 42 of the beginning and end of the zone, respectively, a comparison element 43, registers 44-45, multiplexers 46-47, triggers 48-50, AND elements 51-57, OR elements 58-62, delay elements 63-64. element groups AND 65-72, element groups OR 73-74, clock input 75, trigger input 76, information inputs (buses) 77, address outputs (buses) 78, information outputs 79, outputs (buses) 80-81 of reading permission and records, respectively, and the output of the end of operation of the block.

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Block 40 operates as follows. When the signal arrives at the start input 76 through the AND elements of group 65 from the output 3, the address of the beginning of the zone is written to the counter 41, and the address of the end of the zone of the numbers array recorded in the storage device (memory) of the general destination to be emphasized.

The ordering is that all numbers in the selected bit of which O are moved to the memory at the beginning of the zone, and all numbers in the selected bit of which 1 are moved to the end of the zone. Triggers 48-50 are in the zero state.

The first clock pulse, having entered input 75 and passed through the AND 53 and OR 61 elements, excites the read enable bus 80, and also, passed through the OR 58 element, allows the zone start address from the counter to go through the AND 67 elements and the OR group 73 elements 41 to the output address buses 78 of the device. The signals at these outputs enter the memory, in which the reading of the number recorded at this address takes place, i.e. the first number of the array, which comes from the memory to the output buses 77 of the device and through the And elements of group 71 are written into the register 44 and fed to the inputs of the multiplexer 46, which selects from the number of binary bits, the number of which is supplied from input 4. When the digit 0 is being digitized, a signal appears at the inverse output of the multiplexer 46, which, through the OR element 60, enters the counting input of the counter 41, increasing its content by one, i.e. the address of the next number is written in the counter.

The contents of the counters 41 and 42 are compared by the comparison element 43 when they are equal, at the output 62 a signal appears, a logical unit signaling the end of the unit. This signal also arrives at the inverse input of the And 51 element, closing it and thereby preventing the arrival of clock pulses in the block, in addition, from the register 42 to the output 1 the address of the middle of the zone is received. Otherwise, the operation cycle of the block is repeated.

If the bit of the number to be checked is 1, then a signal appears at the direct output of the multiplexer 46, which switches the trigger 48 to the ON state, transferring the unit 40 from the read mode at the start address to the read mode at the end address. The next clock pulse through the AND 51, 53 and 57 and OR 61 elements drives the read enable bus 40 and allows the band end address from the counter 42 to the output address buses 78 of the block 40 to arrive through the AND element of the group 68 and the OR elements of the group 73

allows writing the last number of the array from the memory through the AND elements of group 72 to the register 45. When the given bit of the number of units is equal, a signal appears at the direct output of the multiplexer 47, which

0 enters through the elements of OR 62 to the counting output of the subtracting counter 42, i.e. the address of the penultimate number of the array of sorted numbers will be written in the counter. Upon receipt of the following clock pulses 5, the operation cycle of block 40 is repeated until a single signal appears on the inverted output of multiplexer 47, which transfers trigger 50 to a single state, thereby switching block 40 to

0 records at the end address. Next, the number is written in a single bit order from register 44 to the memory at the address just read, at which the number with the zero bit selected was located. Another clock pulse through the elements And 53 and And 56 excites the bus 81 records and through the elements And 55 and OR 59 allows the address from the counter 42 to the output address bus 78 of block 40, and from the register

0 44 to the information outputs 79 of block 40, also transfers the trigger 40 to a single state, thereby allowing the signal to pass through element 54 and thereby switching block 40 to the recording mode at address 5 specified by counter 41. When the next clock pulse arrives, block 40 works similarly, outputting the number in the memory from the register 45 to the address specified by the counter 41, and also translates triggers 48-50

0 to the zero state, thereby switching the unit 40 to the number reading mode at the address set by the counter 41. The same pulse delayed by the delay element 63 for the recording time at 40

5 through the delay element 63 for the time of recording the number 40, it enters through the OR element 62 to the input of the counter 42, decreasing its value by one, and delayed by the delay element 64 for the duration of the operation of the OR element

0 62, counter 41 and comparison element 43, enters through the OR element 60 to the input of counter 41, its content is increased by one. Next, the operation cycle of block 40 is repeated with the arrival of the next clock pulse.

The proposed device operates as follows. In the initial state, register 1 contains the address of the beginning of the zone, in register 2 and in the first register of the hardware stack memory 5, the address of the end of the zone of numbers array written to the general-purpose storage device, which must be ordered. The number of M binary digits of the number by which ordering is necessary is recorded in the register of hardware memory | b, starting with the most significant number.

The ordering is that all; the numbers in the high order of which O are moved to the memory at the beginning of the zone, and all the numbers in the high order of which 1 are moved to the end of the zone.

Then this process is repeated separately for zones with zeros and ones in the high order, and the order is carried out in the order with the number one less. The process is repeated until the ordering of the numbers in the memory zones by the least significant, first order is performed. The device repetition logic provides the minimum equipment costs, which are independent of the number of numbers and the number of bits for ordering numbers by the sequence from M to 1 bit numbers.

i When a signal arrives at the start input 39, the contents of register 2 are overwritten through the multiplexer 25 to register 11, the contents of the register 3 are overwritten through the multiplexer 28 into a subtracter and an OR element 20 to the start input of the UR 40, thereby initiating the operation of the device in a disorder mode. The described operation cycles of the device are repeated until the current address of the beginning of the zone of the memory of register 10 becomes equal to the recorded 1 of register 2 of the address of the end of the zone of the entire array of numbers in the memory, which is controlled by the comparison element 7, which generates an equality signal; 58 ending the operation of the device. The end syphal also goes to the inverse input of the element And 18, stopping | thereby accessing clock pulses and device operation.

JB of the proposed device provides | with the ability to order a fixed-format Nickel array recorded in a memory of general purpose for a given number of M high-order bits, in size, The proposed device is distinguished by high speed, mini-number of equipment, not depends on the dimension of the array of numbers and on the number of bits M, according to which the ordering is carried out.

The proposed device can be implemented on standard elements of proz / electronics and computer technology.

The implementation of the proposal is offered in the chromatographic data processing system of the MX-1 microchromatograph.

A meaningful description of the operation of the device is presented in the table.

Claims (3)

SUMMARY OF THE INVENTION 1. A device for arranging an array of numbers, containing start and end of the zone, counters of the beginning and end of the zone, comparison elements, first, second and third registers, first, second and third triggers, eight groups of AND elements, two groups of OR elements, seven AND elements, five OR element, two delay elements, two multiplexers, the i-ro output of the bit of the beginning zone register, where, 2, ..., n, n is the number of bits of the address of the array numbers, connected to the first input of the i-ro of the AND element the first group, the second outputs of the elements And the first group are connected to the input of the device start, the outputs ix of the elements And the first and second groups are connected to the i-th information inputs of the counters of the beginning and end of the zone, the outputs ix of the bits of which are connected to the inputs of the ix bits of the first and the second troupe of information inputs of the comparison element and with the first inputs of the AND elements, respectively, of the third and fourth groups, the outputs of which are connected respectively to the first and second inputs of the i-ro element OR of the first group, the output to torogo is output i-ro discharge device address, comparing the output element is connected to the inverted input of the first AND gate whose output is connected to the first inputs of the second and third AND gates, whose second inputs are connected respectively to inverse and direct outputs of the first trigger, the input of the zero state of which is combined with the input of the zero state of the second trigger, the direct and inverse outputs of which are connected to the first inputs of the fourth and fifth elements, respectively, whose outputs are connected to the first inputs respectively, the first and second elements OR, as well as with the first inputs of the elements And the fifth and sixth groups, the output of the) th element and the seventh group, where 1, 2, ..., t, t is the number of bits of array numbers, is connected to the) -th information input of the first register, outputs jx of bits of the first and the second registers are connected to the second inputs of the jx elements AND, respectively, of the sixth and fifth groups, the outputs of which are connected respectively to the first and second inputs of the j-ro element OR of the second group, the output of which is the j-th information output of the device, the output of the fourth element And connected to the output of the first delay element, the output of the second delay element with the first input of the third OR element, the second inputs of the fourth and fifth elements AND are combined, the first input of the sixth element And is combined with the first input of the seventh element AND, the output of which is connected to the first input of the fourth element AND, the output of the second element OR is connected to the second inputs of the elements of the fourth group, the first inputs of the elements of the second group are combined, the second inputs of the elements of the third group are combined, the output of the 1st bit of the end zone register is connected with the second input of the i-ro element AND of the second group, the outputs of the second and third elements AND are connected to the second inputs of the first and second OR elements, respectively, as well as with the first inputs of the elements AND, respectively, of the seventh and eighth groups, j-th the information input of the device is connected to the second inputs of the j-ro element And the seventh group and the j-ro element And the eighth group, the output of which is connected to the j-th information input of the second register, the outputs jx bits of the first and second registers are connected to the j-th information inputs the first and second multiplexers, respectively, the direct and inverse outputs of which are connected to the unit inputs to the single state of the first and third triggers, respectively, whose zero inputs are connected to the output of the fourth And, the output of the first delay element is connected to the input of the second delay element and the first input of the fifth OR element, the outputs of the third register are connected to the control inputs of the first and second multiplexers, respectively, whose inverse and direct outputs are connected to the second inputs of the third and fifth respectively OR elements, the outputs of which are connected respectively to the summing input of the zone start counter and subtracting input of the zone end counter, the output of the second AND element is connected to the second input of the fourth OR element the output of which is the read permission output of the device, the output of the third AND is connected to the first input of the sixth AND element, the output of which is the write enable output of the device and connected to the second input of the fifth AND element, the output of which is connected to the unit input of the second trigger, the output of the first OR element is connected to the second inputs of the AND elements of the third group, the direct and inverse outputs of the third trigger are connected to the second inputs of the sixth and seventh elements of AND, respectively, the fact that, in order to expand the functionality by ordering an array of numbers in several binary bits, it includes a block for preparing the addresses of the beginning and end of the zone for ordering the array, a block for generating the numbers for the bits for ordering the numbers, a block for storing addresses of zones, a block the memory of the bit number, the second and third comparison elements, the eighth, ninth and tenth AND elements, the first, second and third control elements AND, the sixth and seventh OR elements, the third to sixth delay elements, the third to seventh multiplexers, beats the input of the device is connected to the first input of the eighth element And, the second input of which is connected to the first input of the eighth element And, the second input of which is connected to the output of the second comparison element and the output of the end of the device, and the output is connected to the direct input of the first element And and the first input the first control element And, the output of which is connected to the direct inputs of the ninth and tenth elements of And, the second inputs of which are connected to the outputs of the equalities and inequalities of the second comparison element, respectively, the trigger input is triples is connected to the first control inputs of the unit for preparing the addresses of the beginning and end of the array ordering zone and the unit for generating the order number of the digit and through the third delay element with the first input of the sixth OR element, the output of which is connected to the first combined inputs of the AND elements of the second group, and the second input of the sixth element And is connected to the output of the second control element And, the first input of which is connected to the output of the end of the cycle of the unit for forming the number of the digit ordering number, the second control input the house of the block for preparing the addresses of the beginning and the end of the zone of ordering the array, the second input of the first control element And and the first input of the third control element And, the output of which is connected to the second control input of the unit for forming the number ordering bit number, memory block recording control inputs These are the zone addresses and bit numbers, the first control input of the fifth multiplexer and the third control enter the block for preparing the addresses of the beginning and end of the array control zone, and the second input through the fourth delay element connected to the output of the first element of comparison, the input of the beginning of the cycle of the unit for forming the number of the order of numbers and the first input of the seventh element OR, the output of which through the fifth delay element is connected to the second input of the second control element And, and the second input is connected to the third control the input of the unit for forming the number of the digit ordering number, the second control input of the fifth multiplexer, the output of the ninth AND element and through the sixth delay element with the fourth control input of the unit for generating the number p The order of numbers, the output of the tenth element And is connected to the control inputs for reading the address memory blocks Zones and bit numbers, the information outputs of the first and second groups of the address memory block are connected to the information inputs of the first and second groups of the fifth multiplexer, the outputs of which connected to the information inputs of the first group of the unit for preparing the addresses of the beginning and (end of the array control zone, the outputs of the Zone end counter are connected to the information inputs of the sixth multiplexer, the control input is connected to the output of the third control element AND, and the outputs are connected to the corresponding information inputs of the first group of the fifth multiplexer, the information inputs of the second group of which are combined with the corresponding inputs of the first group of the third comparison element, the inputs of the second group of which are connected to the inputs of the zone end register, with the information outputs of the first group of the block for preparing the addresses of the beginning and end of the zone of ordering the array, combined with the information inputs of the second group of the same block, and the information outputs of the second group of which are connected to the inputs of the zone beginning register and the inputs of the first group of the second comparison element, the inputs of the second group of which are connected to the information outputs of the third group of the unit for preparing the addresses of the beginning and end of the array ordering zone, the outputs of the first group of the memory block of the bit number are connected with information inputs of the third register and moves of the first group of the memory block of the discharge number, information inputs the second group of which is connected to the outputs of the second group of the memory unit of the bit number. 2. The device pop. 1, characterized in that the block for preparing the addresses of the beginning and end of the array control zone contains the beginning and end addresses registers of the array, the first and second output registers and two multiplexers, the outputs of the beginning and end addresses registers being connected to the inputs of the first groups of the first and second multiplexers the first control inputs of which are connected to the first control input of the block, the second control inputs of the multiplexers are the second and third control inputs of the block, and the outputs are connected to the inputs, respectively about the first and second output registers, the outputs of which are information outputs of the third and second groups of the block, information inputs of the first and second groups of the second and first multiplexers, respectively, outputs of the address register of the end Arrays are information outputs of the third block group. 3. The device pop. 1, characterized in that the unit for generating the number ordering number comprises a subtracting unit a counter, two multiplexers, registers of the number and number of bits, the input of the start of the block cycle being connected to the input of the subtracting counter, the overflow output of which is the output of the end of the block cycle; and the outputs of the bits are connected to the information inputs of the first group of the block and the first multiplexer, the information inputs of the second group of which are the information inputs of the second group of the block, the control inputs are the second and fourth control inputs of the block, respectively, and the outputs are connected to the inputs of the register of the bit number yes, the outputs of which are connected to the information inputs the first group of the second multiplexer, the information inputs of the second group of which are connected to the outputs of the register of the number of bits, the control inputs of the first and third control inputs block, and the outputs are connected to the inputs of the bits of the subtracting counter. FIG. 1 d bit A of the number AN 1803909 Az FIG. 2 Si a + J9i fig4