SU1425825A1 - Variable countrown rate frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital frequency synthesis systems with a divider with a fractional division factor. The purpose of the invention, the enhancement of functionality, is achieved by providing the possibility of decreasing or increasing the division factor by an integer while simultaneously increasing speed. The divider contains a pulse counter 1, a code comparison block 2, a shift register 3, a decoder 4, a storage register 5, bus: input 6, control 7, first 8 and second 9 manipulation signals, output 10. In the proposed divider, the speed is the fact that under the action of pulses at the synchronization input of unit 2, it is possible to immediately shift the contents of register 3. 2 Il. § (L

Description

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The invention relates to a pulse technique, in particular to frequency dividers, intended for use in digital frequency synthesis systems with a splitter with a fractional division factor.

The purpose of the invention is the expansion of functional capabilities by providing the possibility of decreasing or increasing the division factor by an integer while simultaneously increasing speed.

Figure 1 shows a structural electrical frequency divider circuit with a variable division factor; Fig. 2 shows a variant of constructing a variable length shift register.

The frequency divider contains a pulse counter 1, a code comparison block 2, a shift register 3, a decoder 4, a storage register 5 (parallel), an input bus 6, an control bus 7, first and second tires 8 and 9 signals

the signal from bus 13, if the control input 14.1 is a logical one, or the signal from the output of the trigger ll.i, if at the control input 14.1 is a logical zero. Thus, applying various combinations of signals to the control inputs 14.1,. .., 14.M-1, it is possible to obtain various signal paths from the bus 13 to the output bus 10 and, thus, to change the discharge d-. register 3 from 1 to M.

The frequency divider works as follows.

The operation of the device is identical cycles. Under the action of the input pulse from the bus 6, a logical unit appears from the output of the register 3 on the bus 10. Counter 1 enters a state in which its counting input is closed and a code is written from bus 7. At the second information input of block 2 and the control inputs of register 3, through register 5, the signal

manipulation and the output bus 10, which is 25 ° scrap from the bus 9. and through the decoder 4, the sigra is connected to the output of the shift register 3 and to the inputs: synchronization of the decoder 4 and the recording of the pulse counter 1 and the storage register 5 The input bus 6 is connected to the clock input the shift register 3, with the synchronization input of the code comparison unit 2 and with the counting input of the pulse counter 1, the information inputs of which are connected to the control bus 7. The first and second groups of information inputs of the code comparison unit 2 are connected to the outputs of the pulse counter 1, respectively.

the storage register 5, the output from the information input of the register 3; with each successive impulse from the bus 6, the contents of the register 3 are shifted by one bit to the left. with a Mr pulse, a logical unit is fed to bus 10 from the output of register 3. Then the next cycle of work begins, proceeding as it was considered. Thus, on bus 10, a pulse with a duration equal to the duration of the input signal period is formed under the action of the edges of the input signal.

the shift input of the shift register 3, the control inputs of which are connected to the outputs of the decoder 4, the information inputs of which are connected to the first bus 8 of the manipulation signal. The information inputs of the storage register 5 are connected to the second manipulation signal bus 9.

Shift register 3 (variable length register) consists of a group of D-flip-flops 11.1, ..., 11.M-1, 11.M and a group of multiplexers 12.1, ..., 12.M-1. The information input 13 of the shift register 3 is supplied with a signal from the output of block 2, and to the control inputs 14.1, ..., 14.M-1 - signals from the output of the decoder 4. To the information input of the trigger 11.1 + 1 through the multiplexer 12.1 comes either

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The number from bus 8 is set to the number with which counter code 1 is compared in block 2, and the frequency of the register is 3. From this moment, the counting of the input pulses begins conditionally. The first impulse from bus 6 sets a logical zero on the output bus 10, the counter 1 starts counting the input pulses from the code installed in it. After the code in counter 1 coincides with that set in block 2, the next pulse generates a logical unit at the output of block 2, which goes to

information entry of the register 3. Each

the smoke from the next pulse from bus 6 registers 3 is shifted one bit to the left. If the register is 3 g-bit, where r varies from 1 to M, then a logical pulse arrives at bus 10 from the output of register 3 . Then the next cycle of work begins, proceeding as it was considered. Thus, on bus 10, a pulse with a duration equal to the duration of the input signal period is formed under the action of the edges of the input signal.

If subtracting counter is used as counter 1, then the division ratio is determined by the formula

N

K + g - 1 + 2,

where K is the direct code of the number on the bus in the corresponding number 1 system; the register size is 3, with g 1, M;

maximum register length 3;

the direct code of the number on pin 9 in the corresponding number 1 system. Let 1 2, M + 3, then the range of the discrete frequency variation of the signal on bus 10 at a fixed K is determined by the expression

14

g M

1 .. f 51, K + M Bbix -

where M is 5: 1, K 1.

The minimum frequency division factor is, „3.

An increase in the speed of a frequency divider with a variable division factor in comparison with the known one is achieved due to the fact that after the appearance of a logical unit, under the action of a pulse at the synchronization input of unit 2, you can immediately shift the contents of register 3, i.e. no time is required to write information in parallel to this register. In addition, the use of D-three in the register 3 with one information input allows the use of elements in these D-triggers of a lower fast-acting than in counter 1.

1425825 F o

rmula of invention

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A variable divider frequency divider containing a pulse counter, the counting input of which is connected to the synchronization input of the code comparison unit, the clock input of the shift register and the input bus, the data inputs to the control signal bus, the bit outputs to the first group of information inputs the code comparison unit, the output of which is connected to the information input of the shift register, the iffepByro manipulation signal bus, characterized in that, in order to extend the functionality while speed boost, and a second manipulation signal bus, a storage register and a decoder are entered, the information inputs of which are connected to the first manipulation signal bus, the outputs from the control inputs of the shift register, the output of which is connected to the synchronization input of the decoder, to the write enable input pulse counter, with the output bus and with the recording input of the storage register, the information inputs of which are connected to the second bus of the manipulation signal; and codes.

Claims (1)

Claim A frequency divider with a variable division coefficient, containing a pulse counter, the counting input of which is connected to the synchronization input of the code comparison unit, with the clock input of the shift register and with the input bus, information inputs - with the control signal bus, bit outputs - with the first group of information inputs of the comparison unit codes, the output of which is connected to the information input of the shift register, the first bus of the manipulation signal, characterized in that · in order to expand the functionality at the same time improving performance, it introduced the second bus of the manipulation signal, the storage register and the decoder, the information inputs of which are connected to the first bus of the manipulation signals, the outputs are with the control inputs of the shift register, the output of which is connected to the synchronization input of the decoder, with an input for recording the pulse counter, with output bus and with the input of the storage register record, the information inputs of which are connected to the second bus of the manipulation signal, the outputs are with the second group of information inputs of the code comparison unit ov.