SU1524037A1 - Device for shaping clock pulses - Google Patents

Abstract

The invention relates to computing and can be used in the design of high-speed digital computing devices with variable speed. The purpose of the invention is to expand the functionality by providing a variable period and duration. The goal is achieved by introducing two groups of blocks 5, 6 comparison, a group of elements And 7, a counter 2. 1 Il.

Description

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The invention relates to computing and can be used in the design of high-speed digital computing devices with variable speed.

The invention is an extension of its functionality by providing a variable period and duration.

The drawing shows a functional diagram of the device.

The device contains a generator of I clock pulses, a counter 2, two registers 3 and 4, two groups of blocks 5 and 6 of comparison, the elementon group 7, the first group 8 of flip-flops 9, the group 10 of flip-flops I, the element 12, a group of 13 outputs of the device.

The device works as follows.

 eerator I produces rectangular and; pulse (pulse period determines the discrete variation of the timing parameters of the clock pulses

which are credited

The input of the counter is 2. The code of the counter 2 is fed to the inputs L of the units 5 and 6 of the comparison. The pulse normalization code is fed from register 3 to the input B of blocks 5 and 6 of the comparison. When the state code of the counter 2 corresponds to the front-front code of the pulse installed at the input B of one of the comparison blocks 5, it will output 1 at its output, which in combination with the unit present at the output of the comparison block 6, will cause a signal at the code M 7 1, which arrives at the information input of the trigger 9. Since the transit time of pulses in different channels due to time variation of the 5 systik may be different, the recording of information in the triggers 9 is clocked by the generator 1 pulses, which eliminates random phase mismatch between sync pulse output at ycTpoficTBa.

When the state code of the counter 2 reaches the value of the code of the back edge of the pulse set at the input B of the corresponding comparison unit 6, an O signal will be output at its output, which will cause the output of the AND element, and therefore, after the tuning of O n ( Wits at the output of the trigger 9, thus, the impulse will be formed one by one

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cash. Similarly, all sync pulses are generated along the remaining channels.

The end of the device operation cycle is the moment of the end of the formation of the last pulse or the moment of the reset of the last trigger 9 to the zero state. This moment is determined using a group of 10 triggers 11 and element 12.

The inputs of the trigger 1 receives pulses from the corresponding outputs of the device. On the backward Auront (decay) of each of these pulses, the triggers 1 1 go to one state.

Thus, at the end of the last clock pulse, all the triggers 11 will be in the one state, and the And 12 element will switch from the zero state to the one state. Since the zero inputs of the flip-flops 11 are connected to the output of the element 12, after a time equal to the sum of the trigger off time of the trigger 1I and the delay time off (the element 12, the element 12 also switches back to the zero state. The received pulse goes to the register recording enable input 4 and to the input g: throw O of the counter 2. At the same time, on the leading edge of this pulse, the new code information from the buffer register 3 will be overwritten into the register 4, and on the falling edge, the counter 2 will return to its initial state, after which e next cycle device operating in sootvepstvii with a new code set in the register 3.

F (T pmu l and inventions

A device for sync pulse shaping, containing a clock pulse generator, two registers, two groups of flip-flops and zlemont I, and the output of the clock impulse generator) Sov is connected to the first group of triggers of the first group, respectively; groups whose outputs (pedalsheni with the inputs of the element 1, the output of which is connected to the input of the recording of the first register, the nionic inputs of which are connected to the outputs of the second register, which group and shrmatsionnyh inputs When you entered the setpoint inputs of the beginning, corner of the device, the recording enable input of the second register is the recording enable input of the device, characterized in that, in order to extend the functionality by providing a variable period and duration, a counter is entered into the device , two groups of comparison blocks and a group of elements, And, the output of the clock pulse generator is connected with the counting input of the estimator, the group of discharge outputs of which is connected to the first groups of information inputs of the comparison blocks The first and second groups, the output of the i-ro comparison unit of the first group (i l ... nj where n is the number of output channels) is connected to the i-th input of the i-ro element AND group, the second input of which is connected to the output of the i-ro block comparing the second group, the output of the i-ro element of the AND group is connected to the information input of the i-ro trigger of the first group, the output of which is the i-th output of the device, the i-group output of the first register is connected to the second group of information inputs of the i-ro block comparison of the first group, (i + l) - the group of outputs of the first register is connected to the second group of infory tional inputs i-ro Neny unit of the second group, output of AND element is connected to the reset input of the counter in C.

Claims (1)

Claim A device for generating clock pulses containing a clock generator, two registers, two groups of triggers and an element And, and the output of the clock generator is connected to the clock inputs of the triggers of the first group: whose outputs are connected respectively to the inputs of the installation in 1 triggers of the second group, the outputs of which are connected the inputs of the AND element, the output of which is connected to the recording permission input of the first register, the information · inputs of which are connected about the outputs of the second register, the group of information INPUTS of which I am a GROUP of inputs for setting the initial conditions of the device, the second record enable input is the device write enable input, characterized in that, in order to expand the functionality by providing a variable period and duration, a counter, two groups of comparison blocks and a group of elements And, and the output of the clock generator is connected to the counting input of the counter, the group of bit outputs of which is connected to the first groups of information inputs of the blocks is compared In the first and second groups, the output of the i-ro unit of comparison of the first group (i = l ... nj where η is the number of output channels) is connected to the i-th input of the i-ro element of the group And, the second input of which is connected to the output i -ro of the comparison block 5 of the second group, the output of the i-ro element of the And group is connected to the information input of the i-ro trigger of the first group, the output of which is the i-th output of the device, the i-th group of outputs of the first register is connected to the second group of information the inputs of the i-ro block of comparison of the first group, (1 +!) - the group of outputs of the first register is connected to the second group of 15 forcing inputs of the i-ro comparison unit of the second group, the output of the AND element is connected to the reset input at 0 of the counter.