SU1157569A1 - Device for recording digital information - Google Patents

Abstract

TO DEVICE FOR RECORDING DIGITAL INFORMATION containing serially connected magnetic head, recording amplifier and counting trigger, pulse shaper, first and second shift registers, information bus and first synchronization bus connected to the information and synchronization inputs of the first shift register, second synchronization bus connected To the first input of the pulse generator, characterized in that, in order to reduce the recording error of the digital information by means of its group synchronization , a pulse counter, a static register, a switch and a feedback signal shaper are entered into it, the pulse counter input and the second pulse driver input are connected to the first clock bus, the pulse driver is connected to the clock input of the second shift register connected to the first and second write inputs respectively, to the output of the pulse counter and the read input of the first shift register, which is connected by an output through a static register to the control input of the switch a, connected by switching inputs to the bit outputs of the second shift register and to the interconnected output of the feedback signal shaper and the information input of the second (L shift register connected to the low and second-last bits of the output of the feedback signal shaper, the output to the input of the counting trigger, and the input of the higher order to the output of the switch. ate and co

Description

2. A device according to claim 1, characterized in that the pulse shaper comprises serially connected first frequency divider, first pulse counter and static register, serially connected second frequency divider and second pulse counter, and a comparison unit, the comparison unit being connected by inputs to the outputs of a static register and the second pulse counter, and the output is connected to the control input of the second counter, which is the output of the pulse former, the first frequency divider is connected by the input to the input v cerned frequency divider, the first input is yuschegos shaper impyv cov, and the first pulse counter clock input is the second input of the pulse shaper.

The invention relates to the field of magnetic recording, in particular to devices for recording digital information.

A device for recording digital information is known, which contains series-connected triggers, elements AND and OR, the last of which is connected to counting trigger 1.

The disadvantage of the device is a significant error in the recording of digital information.

It is also known a device for recording digital information, comprising a serially connected buffer register, a code converter, an output register, a pulse code sequencer, a counting trigger, a recording amplifier, a magnetic recording head, and a synchronization control unit 2.

However, the known device has an accuracy of recording digital information due to insufficient synchronization stability.

The purpose of the invention is to reduce the error of recording digital information by group synchronization.

This goal is achieved in that the device for recording digital information containing serially connected magnetic head, recording amplifier and counting trigger, pulse shaper, first and second shift registers, information bus and first synchronization bus connected to information and synchronization inputs of the first shift register , the second synchronization bus connected to the first inlet of the pulse former, a pulse counter, a static register, a switch and a former are entered feedback, where the input of the counter, pulses and the second input of the pulse generator are connected to the first synchronization width, the pulse generator is connected to the synchronization input of the second shift register, connected to the output of the pulse counter and the read input of the first shift register, respectively, which is connected via an output through a static register to the control input of a switch connected by switching inputs to the bit outputs of the second shift register and to the interconnected output of the feedback signal generator and the information input of the second shift register,

Q connected by the outputs of the younger and penultimate bits to the inputs of the feedback driver, the output to the input of the counting trigger, and the input of the higher order to the output of the switch.

In this case, the pulse shaper contains serially connected first frequency divider, first pulse counter and static register, serially connected second frequency divider and second counter of pulses, and a comparator unit, with the comparison unit connected to the input of the static register and the second pulse counter. , and the output is connected to the control input of the second counter, which is the output of the pulse shaping unit, the first frequency divider is connected to the input to the input of the second frequency divider, The first entrance is formed; pulses, and the clock input of the first pulse counter is the second input of the pulse generator.

, This leads to robust clock and group synchronization when recording digital information.

FIG. 1 and 2 show one of the possible options for a device for recording digital information.

The device contains sequentially

connected magnetic head 1, recording amplifier 2 and counting trigger 3, pulse shaper 4, first and second shift registers 5 and 6, information bus 7 and first sync bus 8 connected to information and synchronization inputs of the first shift register 5, second sync bus 9 connected to the first input of the former 4

pulses. In addition, the proposed device contains a pulse counter 10, a static register 11, a switch 12 and a feedback signal generator 13, the pulse counter 10 input and the second input of the pulse generator 4 are connected to the first clock bus 8. The pulse former 4 is connected by the output to the clock input the second shift register 6 connected by the first and second write inputs respectively to the output of the pulse counter 10 and the read input of the first shift register 5, which is connected to the output via a static th register 11 with control input of switch 12 connected by switched inputs to the bit outputs of the second shift register 6 and to the interconnected output of the feedback signal generator 13 and information input of the second shift register 6 connected to the lower and second to last bits to the inputs driver 13 feedback signals, the output to the input of the counting trigger 3, and the high-level input to the output of the switch 12. The pulse shaper 4 contains 14 hours connected in series the first divider Ota, the first pulse counter 15 and the static register 16, serially connected second frequency divider 17 and a second pulse counter 18 and the comparison unit 19. Comparison unit 19 is connected by inputs to outputs of a static register 16 and a second pulse counter 18. and the output is connected to the control input of the second counter 18, which is the output of the pulse shaper 4. The first frequency divider 14 is connected to the input of the second frequency divider 17, which is the first input of the pulse former 4, and the clock input of the first pulse counter 14 is the second input of the pulse former 4.

The initial information in the form of a serial code on the device information bus, followed by clock pulses on the first clock bus 8, is fed to the input of the first shift register. At the same time, the clock pulses arrive at the pulse counter 10 and the driver of the 4 pulses. Pulse counter 10 counts the number of clock cycles equal to the number of bits in the group of source information to be recoding. In the considered variant, the cycle of work is equal to five cycles. For each fifth clock pulse, a polling signal is generated and the information from the first shift register 5 is written to the static register 11 and to the second shift register 6. Three charges of source information are written in the static register I, and the remaining two, respectively, in the third and fifth bits of the second register 6 shift.

At the same time, a polling signal from the output of the pulse counter 10 in all the even bits of the second shift register 6 records information units, and the remaining bits are zeroed.

Under the influence of the signals of the static register 11 in accordance with the recorded

 By code switch 12 connects the last bit input of the second shift register 6 to either the output of one of the other bits or to the output of the driver 13 of the feedback signals. Further under the influence of

5 pulses, coming continuously from the output of the pulse former 4, information from the output of the second shift register 6 is fed to the counting trigger 3, where the write signal is generated by the BVNM method. With each shift of information in the second

0, the shift register 6, in its least significant bit, records the state determined by the shaper 13 of the feedback signals.

Formed according to the BVNM method, the recording signal from the output of the counting trigger 3 goes to the recording amplifier 2 and then to the magnetic head 1.

The shaper 4 pulses works as follows.

0 Sync pulses with a frequency that is many times higher than the frequency of the generated pulses, are sent to two frequency dividers 14 and 17. The division factors are set equal to the number of bits in the second shift register 6 for the first counter.

 15 pulses and the number of bits in the group of encoded information for the second pulse counter 18 pulses.

Next, the pulses from the output of the first part of the frequency bodies 14 arrive at the input of the first pulse counter 15, the counting time of which is determined by the repetition period of the clock pulses of the input information. With the arrival of each clock pulse on the control input of the first pulse counter 15, its content is transferred to the static register 16, and the first pulse counter 15 is zeroed. The code from the static register 16 is fed to the first inputs of the comparison unit 19, and the second inputs receive the code from 0 outputs of the second counter 18 pulses, to the input of which pulses are output from the second frequency divider 17.

When comparing the values of the codes of the second pulse counter 18 and the static register 16, a pulse is generated at the output of the comparison unit 19, which is fed to the output of the pulse former 4 and to the control input of the second pulse counter 18. Under the action of this pulse, the second pulse counter 18 is zeroed and a new counting cycle begins.

SI

17

U

The use of the invention allows to significantly reduce the error in recording digital information in comparison with the known device.

// m. add

18

-t

r

/9

Tact.

15

0

Ftg.g

Claims (2)

1. DEVICE FOR RECORDING DIGITAL INFORMATION, comprising serially connected magnetic head, recording amplifier and counting trigger, pulse shaper, first and second shift registers, information bus and first synchronization bus connected to information and synchronization inputs of the first shift register, second synchronizing bus, connected to the first input of the pulse shaper, characterized in that, in order to reduce the error in recording digital information by its group synchronization, into it a pulse counter, a static register, a switch and a feedback shaper are introduced, the pulse counter input and the second pulse shaper input connected to the first synchronizing bus, the pulse shaper connected to the synchronization input of the second shift register connected by the first and second recording inputs, respectively, to the counter output pulses and the read input of the first shift register, which is connected by the output through the static register to the control input of the switch, connected by switching inputs to the bit outputs of the second shift register and to the interconnected output of the feedback shaper and the information input of the second shift register connected by the outputs of the lower and last but one bits to the inputs of the shaper of feedback signals, the output to the input of the counting trigger, and the input of the highest bit - to the output of the switch. SU „, 1157569 Figure 1 2. The device according to π. 1, characterized in that the pulse shaper comprises a first frequency divider, a first pulse counter and a static register connected in series, a second frequency divider and a second pulse counter connected in series, and a comparison unit, the comparison unit being connected by inputs to the outputs of the static register and the second pulse counter and the output is connected to the control input of the second counter, which is the output of the pulse shaper, the first frequency divider is connected by the input to the input of the second divider s, which is the first input of the pulse shaper, and the first pulse counter clock input is the second input of the pulse shaper.