SU1332367A2 - Device for detecting the frequency-shift keyed and phase-shift keyed signals of digital information reproduced from a magnetic medium - Google Patents

Abstract

The invention relates to magnetic recording means. The purpose of the invention is to reduce the detection error due to synchronization stability. The pulse counter 16 acts on the decoder 22, which decodes certain of its states. The register 25 controls the decoder 15 through the adder 20. In the presence of temporal distortions in the reproduced signal, the decoder 15 decrypts the predetermined states of the pulse counter 16, taking into account the change in the duration of the time intervals between the pulses of the third pulse sequence. This change determines the delay in relation to the pulses of the third pulse sequence of the pulse generation times of the fourth sequence arriving at the clock inputs of the flip-flops 11 and 14. The trigger signal 11 for each pulse of the fourth pulse-sequence is remembered by the trigger 14. 1 Il. г (Л с с ОО СО Ю СО СО OD N)

Description

The invention relates to magnetic recording, namely, devices for detecting digital information signals manipulated in frequency and phase and reproduced from a magnetic carrier, and is an improvement of the known device according to the author. No. 1195376.

The purpose of the invention is to reduce the linear decoder 15, the delay element 21,

detection resolution due to increased synchronization stability.

The drawing shows a diagram of an apparatus for detecting digital information signals manipulated in frequency and phase and reproduced from a magnetic carrier.

The device contains serially connected magnetic head 1, amplifier Z, filter 3 and vt1) a coupler 4 connected by an output to the corresponding inputs of the first element I 5 through a driver 6 pulses according to signal extremes and a driver 7 pulses according to signal levels, the second 8 and third 9 elements And, the first 10 and second 11 counting triggers, the first 12, second 13 and third 14 triggers, decoder 15, counter 16 pulses and pulse generator 17. The output of the first element And 5 is connected, to one input of the second element And 8 connected to the output of the output The data bus 18. Another input of the second element AND 8 is connected to the output of the first counting trigger 10 and the output clock of the bus 19. The first trigger 12 is connected to the clock and information inputs to the outputs of the driver of the 6 pulses at the extremes of the signal and the driver of the pulses of 7 signal strength. The output of the first trigger 12 is connected to the installation input of the second trigger 13, connected by a synchronization input to the synchronization inputs of the first 10 and second 11 counting triggers and the third trigger 14 and the output of the decoder 15. The output of the second trigger 14 is connected to the first input of the third element And 9 connected by the second input to the output of the third trigger 14 Information input of the third trigger 14 is connected to the output of the second counting trigger 11, connected by the installation input to the third input of the third element And 9 and to the output of the first ementa and 5. The third element

And 9 is connected to the outputs to the installation input of the First counting trigger 10. In this case, the pulse counter 16 is connected to the output of the pulse generator 17.

The device also contains an adder 20, through which the output of the counter 16 pulses is connected to the input

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five

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through the 1st output of the first element I 5 is connected to the installation input of the pulse counter 16, an additional decoder 22, a divider 23, a switch 24 and a register 25. The output of the pulse counter 16 is connected to the inputs of an additional decoder 22 and a divider 23 and with the first information. switch 24 input. The switch 24 is connected to the second information input and the clock input to the outputs of the additional decoder 22 and delig

body 23 and is connected to the output to the information input of the register 25. Register 25 is connected to the clock input to the output of the first element And 5 and is connected to the input of the adder 20.

The device works as follows.

The result of the reproduction from the magnetic carrier comes from the magnetic head 1 through the amplifier 2 and the filter 3 to the rectifier 4, which generates a one-polar signal which is fed to the driver 6 pulses according to the signal extrema, which generates the first pulse sequence, and 0 driver 7 pulses on the level meters of signal, generating a second pulse sequence. The first im-, pulse sequence enters the synchronization input of the first trigger 12, and the second pulse sequence enters its information input. In this case, the first trigger 12 generates impulses of loss.

The first and second pulse sequences also arrive at the first element AND 5, which forms, if they coincide, the third pulse sequence. For each pulse of the third sequence, the pulse counter 13 is set to the zero state and starts counting the pulses of the generator 17 pulses. The value of the pulse frequency of the generator 17 pulses and

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five

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The recalculation factor of the counter 16 pulses is such that the last one clock cycle changes its state from zero to maximum, the Counter 16 pulses affects the additional decoder 22 producing the decryption of its certain states. In the case of a counter transition of 16 pulses of a value equal to 2/3 of its recalculation coefficient, additional decoder 22 forms a potential at which the counter of the pulse counter 16 is connected via divider 23 and switch 24 to the information input of register 25. At the same time, the third pulse of the third pulse sequence the first element And 5 writes in the register

 25 is half the value of the duration of the time interval between the pulses of the third sequence, measured by the pulse counter 16.

If the duration of the time interval between the pulses of the third pulse sequence is less than 2/3 of the conversion factor, then the register 25 records the duration of the time interval between the pulses of the third pulse sequence measured by the pulse counter 16. The register 23 controls the decoder 15 through the adder 20. In the absence of temporal distortions in the reproduced signal, the decoder 15 forms a fourth pulse sequence corresponding to twice the frequency of the bits and delayed relative to the pulses of the third sequence by a quarter of the clock period.

If there are temporal distortions in the reproduced signal, the decoder 15 performs decoding of the specified states of the pulse counter 16, taking into account the change in the duration of the time intervals between the pulses of the third pulse sequence. This change determines the delay in relation to the pulses of the third pulse sequence of pulse generation times of the fourth sequence arriving at the clock inputs of the second counting trigger 11 and trigger 14. The second counting trigger 11 is shifted to the zero state by pulses of the third sequence and switches each impulse of the fourth sequence. The signal of the second counting trigger 11 for each pulse of the fourth pulse sequence is memorized by the third trigger 14.

The pulses from the first trigger 12 arrive at the second trigger 13, transferring it to the zero state. The second trigger 13 retains the zero state until the first pulse of the fourth pulse sequence after the end of the fallout pulse transfers it to the single state. The signals from the second 13 and third 14 flip-flops and from the first element And 5 arrive at the third element And 9. In case of coincidence of these signals, the third element And 9 generates pulses that bring the first counting trigger 10 into the zero state. The first counting trigger 10 switches over each pulse of the fourth pulse sequence and generates pulses supplied to the output clock bus 19 and to the second element AND 8. In the second element And 8 there is a gating of the third pulse sequence ensuring the formation of information logic units arriving at the output information bus 18.

Claims (1)

Apparatus of the Invention A device for detecting frequency and phase manipulated digital information signals reproduced from a magnetic carrier by author. N 1195376, characterized in that, in order to reduce error-detection by increasing synchronization stability, an adder is entered into it through which the output of the pulse counter is connected to the input of the decoder, a delay element through which the code of the first element I is connected to the installation input of the counter of pulses , additional decoder, divider, switch and register, with the output of the pulse counter connected to the inputs of the additional decoder and divider and to the first information input of the switch connected to Odom vkodam respectively to additional de shfratora and divider and the output is connected to the information 51332367v the input of the register, which is connected to the first element And and is connected to the output-synchronization input to the output of the house with the input of the adder. Compiled by Yu.Royenkrantz Editor V.Petrash Techred M.DidykKorrektor S.Cherni Order 3838/47 Circulation 589 Subscription VNIIPI USSR State Committee on affairs of inventions and discoveries 113035, MoskvarZh-35, Raushsk nab., d. 4/5 I Production and printing company, Uzhgorod, st. Design, 4.