SU1324067A2 - Device for detection of frequency- and phase=keyed signals of digital information reproduced from magnetic carrier - Google Patents

Abstract

This invention relates to magnetic recording. The purpose of the invention is to reduce the detection error when a signal falls out due to the current control of the error rate. At the inputs of the element And 13 there are signals from the outputs of the flip-flops 15 and 16 and the element And 8. When these signals coincide, the element And 13 generates pulses that zero the trigger 11, switching over each pulse of the fourth sequence and forming the clock signal arriving at bus 12 and the input element I 9. The clock signal gates the element 9 and the pulse sequence and generates the pulses arriving at the bus 10. Pulses from the output element And 21 overwrites the register 23 calculated by the adder 24 sums yduschego state register 23 and the current state of the counter 25. The register 23 accumulates information about the number of clock pulses corresponding to the m signal falling out. 1 nl with JV with GS about and ISJ

Description

The invention relates to magnetic recording, in particular, to devices for detecting digital information signals manipulated in frequency and phase and reproduced from a magnetic carrier.

The aim of the invention is to reduce the detection error in the event of signal drops due to the monitoring of the error rate.

The drawing is given a functional diagram of the proposed device.

The device contains a playback unit 1 consisting of a magnetic head 2 connected in series, an amplifier 3, a filter 4 and a rectifier 5 connected by an output through pulse shapers according to extremums 6 and by signal levels 7 to the corresponding inputs of the first element I 8 connected by an output to one input of the second element And 9, connected by an output with the information bus 10 and another input .- with the output of the first counting trigger 11 and with the synchronization time

12. The device contains the third element AND

13, first 14, second 15 and third 16 triggers, pulse generator 17, pulse counter 18, decoder 19, second counting trigger 20. First trigger 14 is connected by synchronization and information inputs to the outputs of the drivers 6 and 7, respectively, and the output to the installation input the second trigger 15 connected by the synchronization input with the synchronization inputs of the second counting trigger 20, the third trigger 16 and the first counting trigger 11 and the output of the decoder 19, and the output with the first input of the third element And 13, the second input of the of the third trigger 16, the information input of which is connected to the output of the second counting trigger 20, the installation input connected to the third input of the third element I 13 and to the interconnected installation output of the decoder 19, and the installation input through the delay element 26 is connected to the output of the first element and 8.

The device in the process of forming

g rd pulse sequences. The reproduced, amplified and filtered signal from the output of playback unit 1 enters the shaper 6 through the extremes, which forms the first pulse sequence, and the shaper 7, according to the signal levels, which forms the second pulse sequence. The first sequence arrives at the trigger input of trigger 14, and the second at its information input. On

with the output of the trigger 14, impulses are formed. The first and second sequences are also fed to the inputs of the And 8 element, which at the moments of their coincidence forms the third pulse sequence. For each pulse of this sequence, the counter 18 is zeroed and the high frequency generator oscillator 17 starts counting. The oscillator frequency 17 and the recalculation factor of counter 18 are chosen such that the output of the decoder 19 generates a fourth pulse sequence of the doubled clock frequency delayed by a quarter of the third clock pulse sequences. The pulses of the fourth sequence arrive at the clock inputs of the flip-flops 16 and 20. The trigger 20 is zeroed by the pulses of the third sequence and switches on each pulse of the fourth sequence. The output signal from trigger 20 for each pulse of the fourth sequence is remembered on trigger 16. At the same time, the pulses from the output of trigger 14 zero the trigger 15, which keeps the zero state at the output until the first pulse from the fourth sequence after the end of the pulse of fallout

20

25

thirty

35

45

The input of the pulse counter 18 and the output 40 will not set a high potential at the output of the first element And 8. The third element And 13 15. is connected by an output to the installation input of the first counting trigger 11, and the counter 18 of pulses is connected by an input to the output of the generator 17 pulses and the output - the input of the decoder 19. In addition, the device contains a fourth element And 21, the element is NOT 22, the register 23, the adder 24, an additional counter 25 pulses, the element 26 of the delay. The fourth element And 21 is connected by one input through the element NOT 22 to the output of the second trigger 15 and the other input to the output of the first element And 8, and the output is connected to the clock input of the register 23 connected by the output to one input of the adder 24 connected to the information input 55 delays, for example, one clock-period 23, and another input - to the output of the generator generator 17, the counter 25, an additional pulse counter 25, is zeroed, the synchronization input of which is connected to the fourth the sequences inside the InterTakm, at the inputs of AND 13 there are signals from the outputs of the flip-flops 15 and 16 and the element AND 8. When these signals coincide, the element AND 13 forms impulses that trigger 11. is flushed. Trigger 11 switches on each pulse of the fourth sequence and generates a sync signal arriving at bus 12 and at the input of the E-element 9. The sync-50 signal gates on element 9 the third pulse sequence and generates pulses of information “units arriving at bus 10.

At the same time, the third sequence pulses delayed on the element 26

the output of the decoder 19, and the installation input through the element 26 of the delay is connected to the output of the first element And 8.

The device in the process of forming

a series of pulse sequences. The reproduced, amplified and filtered signal from the output of playback unit 1 enters the shaper 6 through the extremes, which forms the first pulse sequence, and the shaper 7, according to the signal levels, which forms the second pulse sequence. The first sequence arrives at the trigger input of trigger 14, and the second at its information input. On

with the output of the trigger 14, impulses are formed. The first and second sequences are also fed to the inputs of the And 8 element, which at the moments of their coincidence forms the third pulse sequence. For each pulse of this sequence, the counter 18 is zeroed and the high frequency generator oscillator 17 starts counting. The oscillator frequency 17 and the recalculation factor of counter 18 are chosen such that the output of the decoder 19 generates a fourth pulse sequence of the doubled clock frequency delayed by a quarter of the third clock pulse sequences. The pulses of the fourth sequence arrive at the clock inputs of the flip-flops 16 and 20. The trigger 20 is zeroed by the pulses of the third sequence and switches on each pulse of the fourth sequence. The output signal from trigger 20 for each pulse of the fourth sequence is remembered on trigger 16. At the same time, the pulses from the output of trigger 14 zero the trigger 15, which keeps the zero state at the output until the first pulse from the fourth sequence after the end of the pulse of fallout

0

five

0

five

0 will not set a high potential at output 15. 5 delays, for example, for one frequency generator oscillator frequency 17, zero counter 25, which counts the fourth sequence pulses within the inter-

will not set a high potential at the output 15. Delays, for example, for one period of the frequency of the generator 17 nullify the counter 25, which performs the counting of the fourth-sequence pulses within the interCons, the inputs from the And 13 element contain signals from the outputs of the trigger 15 and 16 and element 8. If these signals coincide, element 13 forms impulses that trigger trigger 11. Trigger 11 switches over each pulse of the fourth sequence and generates a sync signal fed to bus 12 and to input of an element 9. The chro signal gates on the And 9 element the third pulse sequence and generates the impulses of information “units arriving on the bus 10.

At the same time, the third sequence pulses delayed on the element 26

shafts between the pulses of the third sequence. In this case, the pulses from the output of the trigger 15 are inverted on the element HE 22 and gated on the element 21 and the third pulse sequence. As a result, at the output of the element 21, pulses are formed corresponding to the first extremums of the signal after the end of the fallout mode, which are fed to the synchronizing input of the register 23. The pulses from the output of the element 21 are rewritten into the register 23 by the sum of the previous register 23 and current the state of the counter 25. Thus, in the register 23, information is accumulated on the number of clock pulses corresponding to the loss of the signal.

Claims (1)

Invention Formula Apparatus for detecting frequency and phase manipulated signals 20 Editor t. Parfenova Order 2970/54 VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 five 0 digital information reproduced from magnetic media, by author. St. No. 1195376, characterized by the fact that, in order to reduce the detection error during a signal fallout due to the current monitoring of the error rate of the reproduced information, the fourth element AND, the element NOT, the register, the adder, the additional pulse counter and the delay element are entered into it, and the fourth element And connected by one input through the element NOT to the output of the second trigger, and the other input to the output of the first element AND and the output connected to the clock input of the register connected by the output to the first input of the adder, Connecting to the output data input register and the second input - to the output of the additional pulse counter connected to the synchronizing input and output deschifratora adjusting input via a delay element - to the output of the first element I. Compiled by V. Dobrovo.lsky Tehred I. Veres Corrector A. Ilyin Circulation 589 Subscription