SU1383405A1 - Interpolator - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the reliability of interpolation in the presence of single distorted samples. The interpolator contains a generator 1 clock pulses, a delay block 2, a two-threshold comparator 3, an algebraic adder 4, a switching block 5, an analog interpolation block 6, a D-flip-flop 7, an And 8 element, an input 9, an output 10. When a distorted input value appears whose deviation from the neighboring one exceeds the tolerance set by the comparator, it is replaced by the average value calculated by the neighboring values. 1 Il. i (Л С

Description

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The invention relates to computing.

The purpose of the invention is to increase the reliability of interpolation in the presence of single distorted samples.

The drawing shows the proposed interpolator.

The interpolator contains a clock generator, a delay unit 2, a two-threshold comparator 3, an algebraic adder 4, a switching unit 5, an analog interpolation unit 6, a D-flip-flop 7, an AND 8 element, an input and an output 10.

The interpolator works as follows.

In the interpolator, in the presence of single distorted samples, error detection is performed by determining the signal increment between two adjacent samples in a subsequent comparison of this increment with the tolerance. The tolerance is determined by the maximum possible rate of change of the input signal. If the signal increment is higher than the tolerance, the sample is considered distorted and is replaced by the value calculated by the interpolation polynomial formula of degree N. This uses a hectare of undistorted counting preceding the distorted one and n samples following the distorted one.

Signals are input to input 9 with a period T, which are recorded in delay block 2 on the leading edge of clock pulses. When a distorted sample appears at the main output of the delayed sample, the difference between it and the neighboring sample exceeds the tolerance and the signal of the logical unit appears at the output of the comparator 3. The inverting output of the D-flip-flop has a logical unit before the next clock pulse arrives. Therefore, the element I, acting on the switching unit 5, connects the output of the algebraic adder 4 to

Compiled by G. Editor N. RogulichT.Gred M. Didyk

Order 1298/50

Circulation 704

the input of block 6, replacing the distorted input value with the calculated in I algebraic adder 4 on the neighboring, undistorted values. Then the D-flip-flop on the leading edge of the sync pulse is switched to the opposite state, and the output of the And 8 element appears zero and the main output

The unit 2 is connected again to the input of unit 6.

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Claims (1)

Invention Formula 5 An interpolator containing a delay unit whose input is the input of an interpolator, a clock generator whose output is connected to the synchronization inputs of the delay unit and an analog interpolation unit, an algebraic adder, whose inputs are connected to the output group of the delay unit, and the output - with the first information input of the switching unit, the output of which is connected to the information input of the analog interpolation unit, the output of which is the interpolator output, characterized in that 0 for increasing the interpolation reliability in the presence of single distorted samples, the interpolator contains a two-threshold comparator, a D-trigger and an AND element, with the main output 5 of the delay unit is connected to the second information input of the switching unit and the first input of the two-threshold comparator, the second input of which is connected to the output of the group of outputs of the unit 0 delay, which is characterized by a delay, one step more than the delay on the main output of the block zhlderzhki, the output of the two-threshold comparator is connected to the information input of the D-flip-flop and the first input of the element And, the output of the clock generator is connected to the synchronizing input of the D-flip-flop, and its inverse input - with the second input of the element AND, .the output of which is connected to the control input of the switching unit sipov   Proofreader M. Maksimishinets  Subscription