JPH0370314A - Clock interrupt detection circuit - Google Patents

Abstract

PURPOSE:To set a signal period setting a detection period optionally by providing a 2nd D flip-flop block reading an output signal being interrupt detection information of a 1st D flip-flop block receiving an output signal of an interrupt detection period signal generating circuit as a clock signal. CONSTITUTION:An output signal S6 of an interrupt detection period signal generating circuit 7 is inputted to a 1st D flip-flop block 8 and a 2nd D flip-flop block 9 as a clock signal. The 1st D flip-flop block 8 receives an interrupt detection object clock signal S7 as a reset signal and an output signal S8 of the 1st D flip-flop block 8 is read to the 2nd D flip-flop block 9 as interrupt detection information. Thus, the signal period setting the detection period is not limited by the interrupt detection object clock signal but set optionally with an inexpensive circuit constitution of clock interrupt detection circuit.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock interruption detection circuit that detects an interruption state of a clock signal and sends out clock interruption information, the signal period for setting the detection period is limited to the clock signal to be detected as interruption. The purpose of this invention is to provide a clock disconnection detection circuit with an inexpensive circuit configuration that can be arbitrarily set without any interruption.In a clock disconnection detection circuit that detects an intermittent state of a clock signal, a disconnection detection period signal that outputs a signal to set the disconnection detection period is provided. a first D-type flip-flop block to which the clock signal to be detected as a disconnection detection target signal is input as a reset signal and the output signal of the disconnection detection periodic signal generation circuit is input as a clock signal; The output signal is input as a clock signal and the first D
A second D-type flip-flop block is provided which reads the output signal of the D-type flip-flop block as disconnection detection information.

[Industrial Application Field] The present invention relates to a clock disconnection detection circuit that detects a clock signal disconnection state and sends out clock disconnection information. This invention relates to a disconnection detection circuit.

In multiplex data transmission systems and the like, multiple systems of clock signals may be selectively switched and used using a selector or the like.

In such a system, it is necessary to always know whether or not each system's clock signal is being sent.

Therefore, a clock disconnection detection circuit is used that detects the disconnection state of the clock signal and sends out clock disconnection information.

[Prior Art] FIG. 4 is a block diagram showing an example of a conventional lock disconnection detection circuit. In the figure, a timer circuit 1 outputs a signal S1 for setting a clock interruption detection period, and this output signal S is input to a frequency dividing circuit 2. The output signal S2 of the frequency dividing circuit 2 is input to the reset terminal length of the D-type flip-flop 5 via the inverter 3 and the buffer 4, and is also input to the reset terminal length of the D-type flip-flop 6.
It is input to clock terminal C of . The clock terminal C of the D-type flip-flop 5 receives an external clock signal S,
is input, the data terminal is fixed at H level, and the output signal S4 of the output terminal Q is input to the data terminal of the D-type flip-flop 6. The output signal S, at the output terminal Q of the D-type flip-flop 6 is sent out as clock signal S, disconnection information.

The operation of such a circuit will be explained using the timing chart of FIG.

The timer circuit 1 outputs a signal S1 as shown in (a) to the frequency dividing circuit 2 for setting a clock interruption detection period. The frequency dividing circuit 2 divides the input signal S1 by l/+ to set a detection period, and for each detection period, as shown in (b), a signal S2 with a pulse width equal to the pulse width of the signal S1 is generated. Output. The output signal S2 of the frequency dividing circuit 2 is sent to the inverter 3.
is input as a reset signal to the set terminal of the D-type flip-flop 5 via the buffer 4, and is also input as a clock signal to the clock terminal C of the D-type flip-flop 6, but the reset terminal length of the D-type flip-flop 5 A series circuit of an inverter 3 and a buffer 4 provides a sufficient delay time for the reset signal inputted to the rising edge of the clock signal inputted to the clock terminal C of the D-type flip-flop 6. A clock signal S3 to be detected as shown in (C) is input from the outside to the clock terminal C of the D-type flip-flop 5. (d
) indicates the output signal S4 of the D-type flip-flop 5. The output signal S4 of the flip-flop 5 is reset to the L level by inputting the output signal S2 of the frequency dividing circuit 2, but it is different from the normal one in which the clock signal S3 is continuously inputted. state, the next clock signal S.

It is set at the rising edge of the signal and immediately goes to H level. However, in the off state where the clock signal S is fixed so that either the H level or the L level is continuous, the signal S
The reset state is maintained from the rising edge of clock signal S until the clock signal S returns to its normal state. (e) shows the output signal S of the D-type flip-flop 6.

That is, the D-type flip-flop 6 is connected to the frequency dividing circuit 2.
Using the output signal S2 of the D-type flip-flop 5 as a clock, the output signal S4 of the D-type flip-flop 5 is outputted as read-out information.

[Problems to be Solved by the Invention] However, in such a conventional circuit configuration, the output signal S1 of the timer circuit 1 is divided by the frequency dividing circuit 2 to generate a reset signal for the D-type flip-flop 5. Therefore, the speed is limited due to the relationship with the cycle of the clock signal S3, which is the object of disconnection detection.

Therefore, it is not possible to freely change the period for detecting the interruption of the clock signal, and the period of the output signal S1 of the timer circuit 1 must be fixed.

Furthermore, when the clock signal S3 to be detected as disconnection becomes faster, the output signal S1 of the timer circuit 1 must also be made faster, so a highly accurate oscillation element must be used as the oscillation element of the timer circuit 1, which increases the cost of the circuit. There is also the issue of becoming.

The present invention has been made in view of these problems, and provides a clock loss detection circuit with an inexpensive circuit configuration in which the signal period for setting the detection period can be arbitrarily set without being limited to the clock signal to be detected. The purpose is to provide.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of a clock disconnection detection circuit according to the present invention. In the figure, the output signal S6 of the disconnection detection period signal generation circuit 7 is input as a clock signal to a first D-type flip-flop block 8 and a second D-type flip-flop block 9. The first D-type flip-flop block 8 is supplied with a clock signal S7 to be detected as a reset signal. The output signal S8 of the first D-type flip-flop block 8 is read into the second D-type flip-flop block 9 as disconnection detection information.

[Function] The first D-type flip-flop block 8 receives the output signal S6 of the disconnection detection periodic signal generation circuit 7 as a clock signal, and inputs the disconnection detection target clock signal S7 as a reset signal. By setting the period of the output signal S6 of the periodic signal generating circuit 7 to be longer than the period of the clock signal S7 to be detected, the first D-type flip-flop block 8 is always in a reset state.

Then, when the disconnection detection target clock signal S7 becomes disconnected, the first D-type flip-flop block 8 is not reset, and disconnection detection starts at the rising edge of the output signal S6 of the disconnection detection cycle signal generation circuit 7, and the disconnection detection state is reached. continues for one period or more, the output signal S8 of the first D-type flip-flop block 8 becomes the second D-type flip-flop block 8 as disconnection detection information.
type flip-flop block 9.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.

In the figure, a timer circuit 7, which is a disconnection detection cycle setting signal generation circuit, inputs a disconnection detection cycle signal S6 to a first D-type flip-flop block 8 and a second D-type flip-flop block 9 as a clock signal. The first D-type flip-flop block 8 is composed of two D-type flip-flops 10 , 11 , an inverter 12 and an OR gate 13 . The data terminals of each flip-flop 10 and 11 are fixed at H level, the output signal S6 of the timer circuit 7 is input to the clock terminal C, and the output signal is input to the OR gate 13. The length of the reset terminal of the D-type flip-flop 10 is connected to the clock signal S to be detected.
7 is directly input, and a disconnection detection target clock signal S7 is input to the reset terminal length of the D-type flip-flop 11 via an inverter 12. The output signal S of the OR gate 13 is connected to the data terminal of the second D-type flip-flop 9.
8 is input, and the output signal S6 of the timer circuit 7 is input to the clock terminal C.

The operation of such a circuit will be explained using the timing chart of FIG.

The timer circuit 7 sends a clock signal S6 as shown in FIG. Enter as . The reset terminal length of the D-type flip-flop 10 is (b
) is directly inputted, and the reset terminal length of the D-type flip-flop 11 is supplied with a signal S, which is obtained by inverting the clock signal S7 to be detected by an inverter 12, as shown in (c). has been entered. (
d) shows the output signal SI+ of the D-type flip-flop 10, and (e) shows the output signal SI of the D-type flip-flop 11.
2 is shown. Each type fritub flop 1.0.11
The output signal S I l+ 512 is set by inputting the output signal S6 of the timer circuit 7 as a clock signal to the clock terminal C, but in the normal state where the clock signal S7 to be detected is continuously inputted. Then, it is immediately reset by the next disconnection detection target clock signal 37,510. However, the disconnection detection target clock signal S7
For example, in the off state where the L level is fixed as shown in (b), the output signal S of the D type flip-flop 10 remains in the set state, and the output signal S+Z of the D type flip-flop 11 is From the rising edge of the output signal S6 of the timer circuit 7, the clock signal S to be detected is turned off.
The set state is maintained until 7 returns to the normal state. As a result, the disconnection detection target clock signal S7 goes to H level.

The disconnection state can be reliably detected even if the disconnection occurs at any of the L levels. (f) shows the output signal S8 of the OR gate 13. The second D-type flip-flop block 9 clocks the output signal S8 of the OR gate 13 when the disconnection detection state of the output signal S8 of the OR gate 13 continues for one cycle or more of the clock disconnection detection period signal S6 shown in (a). It is read as disconnection information and output as shown in (g).

With this configuration, since the output signal S6 of the timer circuit 7 is used as it is as the clock interruption detection period signal, it can be varied over a wide range.

Furthermore, even if the clock signal S7 to be detected as a clock signal S7 becomes faster, the output signal S6 of the timer circuit 7 does not need to be made so fast, and a low-speed oscillation element can be used. Can be done cheaply.

Furthermore, since the conventional frequency dividing circuit is not required, the circuit scale can be reduced.

[Effects of the Invention] As explained in detail above, according to the present invention, the clock loss detection can be performed using an inexpensive circuit configuration in which the signal period for setting the detection period can be arbitrarily set without being limited to the clock signal to be detected. The circuit can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a timing chart for explaining the operation of Fig. 2, and Fig. 4 is a conventional clock. FIG. 5 is a block diagram showing the entire disconnection detection circuit, and FIG. 5 is a timing chart for explaining the operation of FIG. 4. In FIG. 1, 7 is a detection period setting signal generating means, 8 is a first D-type flip-flop block, and 9 is a second D-type flip-flop block.

Claims (1)

[Claims] A clock interruption detection circuit that detects an intermittent state of a clock signal includes an interruption detection period signal generation circuit (7) that outputs a signal for setting an interruption detection period, and an interruption detection period signal generating circuit (7) that outputs a signal for setting an interruption detection period, and a clock signal to be detected as an interruption detection circuit as a reset signal. A first D-type flip-flop block (8) receives the output signal of the disconnection detection period signal generation circuit (7) as a clock signal, and the output signal of the disconnection detection period signal generation circuit (7) receives the output signal as a clock signal. A clock disconnection detection circuit comprising a second D-type flip-flop block (9) which is input as a signal and reads the output signal of the first D-type flip-flop block (8) as disconnection detection information.