JPH04178047A - Skew compensation system - Google Patents

Abstract

PURPOSE:To realize excellent parallel data transmission by providing a skew measuring signal pattern detection circuit and skew detection circuit, a control circuit and a skew compensation circuit in the system to obtain a data subject to skew compensation. CONSTITUTION:When a receiver group of a receiver side receives a data from a driver group of a sender side via a transmission line 14, a clock counter group 19 of a skew measuring signal pattern detection circuit and skew detection circuit 23 measures a delay between data with most advanced phase. A control circuit 25 sends an H level gate signal an AND circuit group 24 based on a count stored in a memory 20 and a minimum count. One of AND circuits 24 receiving each parallel output of a register group 22 is set by a gate signal from the circuit 25 and a data subject to skew compensation is outputted from an OR circuit 26. Thus, the skew caused by various causes is compensated.

Description

[Detailed Description of the Invention] [Summary] Regarding a skew compensation method that performs skew compensation for parallel transmission data, an object of the present invention is to provide a skew compensation method that can perform good parallel data transmission by compensating for skew. A skew measurement signal pattern detection circuit and skew value detection circuit that receives predetermined fixed data from the transmitting side and detects the amount of delay with respect to the most phase-advanced data, and the skew measurement signal pattern detection circuit. A control circuit that outputs a control signal that compensates for each detected delay amount based on the detected delay amount, and a skew compensation circuit that selects and outputs data skew compensated by the control signal from among its parallel outputs. and configure it to obtain skew-compensated data.

[Industrial Application Field] The present invention relates to a skew compensation method for skew compensating parallel transmission data.

In parallel data transmission, when the transmission distance is long or the transmission speed is high, skew between each data item may become a problem. In such a case, it is necessary to compensate for the skew to ensure good parallel data transmission.

[Prior Art] For example, as shown in FIG. 3, parallel data DO to Dn transmitted from the transmitting side are input to a receiver 1.2, and a flip-flop 3, to which clocks are input from the receivers 1 and 2, respectively. 4, as shown in FIG. The margin becomes smaller due to the occurrence of skew.

Conventionally, skew was measured using, for example, a logic analyzer, and if the skew was within a certain value, parallel data was transmitted to perform skew compensation.

[Problem to be solved by the invention] However, in such conventional parallel data transmission methods, when skew occurs due to various causes, skew is not compensated for, so it is difficult to achieve good parallel data transmission. There was a problem that I could not do it. Also,
There was a limit to transmission distance due to skew, or an upper limit to transmission speed.

The present invention has been made in view of such conventional problems, and is a skew compensation method that can realize longer distance, faster, and better parallel data transmission by compensating for skew. The purpose is to provide a method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 23 is a skew measurement signal pattern detection circuit and skew value detection circuit that receives predetermined fixed data from the transmitting side and detects the amount of delay with respect to the data with the most advanced phase, and 25 is a skew measurement signal pattern detection circuit and skew value detection circuit. A control circuit outputs a control signal that compensates for each delay amount detected by the signal pattern detection circuit and skew value detection circuit 23, and 27 outputs a control signal that compensates for the delay amount based on the delay amount detected by the signal pattern detection circuit and skew value detection circuit 23; This is a skew compensation circuit that selects and outputs the selected data.

[Operation] In the present invention, predetermined fixed data is received from the transmitting side, the amount of delay between the data with respect to the data with the most advanced phase is detected, and the amount of delay is compensated based on this amount of delay. A control signal is given to the skew compensation circuit. The skew compensation circuit selects and outputs data skew compensated by the applied control signal from among the parallel outputs of the shift register.

Therefore, even if skew occurs due to various causes in the transmission of parallel data, it is possible to compensate for the skew, thereby achieving good parallel data transmission.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In FIG. 2, 11 is a skew measurement signal pattern generation circuit on the transmitting side, and the skew measurement signal pattern generation circuit 11 generates fixed data for skew measurement.

As fixed data for skew measurement, for example, the same data stream is sent to all parallel bits, and the data is a series of "0"s and "1s" that are predetermined to be impossible as input data. There is a repeating signal.

12 is a switching control circuit, and the switching control circuit 12 performs switching control between input data and fixed data.

The input data or fixed data switched by the switching control circuit 12 is transmitted by the driver group 13 from the transmission path 4 to the receiving side.

15 is a receiver group on the receiving side, and the receiver group 15 receives data from the triver group 13 on the transmitting side and outputs it to the flip-flop group 16. Each output of the flip-flop group 16 is latched by a latch circuit 18 via an OR circuit 17, and a clock counter group 19 starts counting by the output of the latch circuit 18. Falling signal sPO of flip-flop group 16 before input to OR circuit 17
SPn is input to the clock counter group 19, respectively, and the clock counter group 19 stops counting.

Therefore, the clock counter group 19 measures the amount of delay with respect to the data (0 to n) whose phase is most advanced. Each count value of the clock counter group 19 is stored in the memory 2.
Stored as 0.

21 is a clock source, and the clock source 21 supplies clocks to the flip-flop group 16, the clock counter group 19, and the shift register group 22, which will be described later.

The frequency of the clock source 21 is set higher than the data rate to be transmitted. The degree of compensation is determined depending on the step value of the skew to be compensated, but here it is set to about 10 times the data rate.

Flip-flop group 16, OR circuit 17, latch circuit 1
8, the clock counter group 19, the memory 20, and the clock source 21 collectively constitute a skew measurement signal pattern detection circuit and skew value detection circuit 23 that detects the skew measurement signal pattern.

22 is a shift register group;
are respectively connected to the flip-flop group 16 and operate with the same clock as the flip-flop group 16. Each parallel output of the shift register group 22 is input to an AND circuit group 24, and a gate signal from a control circuit 25 is input to the AND circuit group 24. The control circuit 25 sends a predetermined gate signal to the AND circuit group 24 so as to compensate for the amount of delay based on each count value from the clock counter group 19 stored in the memory 20.

AND circuit group 24 by a gate signal from control circuit 25
One of them is turned on, and skew-compensated data is output from the OR circuit 26.

Although not shown, an AND circuit group 24 and an OR circuit 26 are connected to the shift register group 22, respectively. The shift register group 22, the AND circuit group 24, and the OR circuit 26 collectively constitute a skew compensation circuit 27 that performs skew compensation.

Next, the operation will be explained.

First, the signal pattern generation circuit 1 for measuring skew on the transmitting side
] generates fixed data, the switching control circuit 12 switches to the fixed data, and the driver group 13 is driven with the same data (all "0"-"1").

On the receiving side, data from the driver group 13 on the transmitting side is received by the receiver group 15 via the transmission path 14, and sampled by the flip-flop group 16. Flip-flop group 1
6 is latched by a latch circuit 18 via an OR circuit 17, and this latch output causes the clock counter group 1 to
Start counting to 9. In other words, all data is 0
The clock counter group 19 starts counting at the earliest timing of "1" among n. Then, the falling signals SPO to SP of the flip-flop group 16
Counting of the clock counter group 19 is stopped by n.

This allows the clock counter group 19 to measure the amount of delay between data with respect to the data whose phase is most advanced.

Each count value of the clock counter group 19 is stored in the memory 20 and used for skew compensation of each data.

Based on each count value stored in the memory 20, the control circuit 25 sends an H level gate signal to the AND circuit group 24 so as to compensate for the amount of delay based on the minimum count value.

Among the AND circuits 24 to which each parallel output of the shift register group 22 is input, one is turned on by a gate signal from the control circuit 25, and the OR circuit 26 outputs skew-compensated data.

In this way, in parallel data transmission, it is possible to compensate for skew caused by various causes, and thus it is possible to realize good parallel data transmission.

Note that since this sequence is always passed when the device is powered on, it is possible to cope with changes in the skew value over time without any problem. Further, if the skew value changes due to a change in the device environment temperature and transmission cannot be performed normally, a sequence for resetting the skew compensation value is entered, so that it is possible to cope with temperature fluctuations.

In this example, the operation was explained by counting the clock from the rising edge to the falling edge of the skinny measurement signal pattern. Of course, it is also possible to operate by counting the clock to the falling edge of each data.

[Effects of the Invention] As described above, according to the present invention, even if skew occurs when transmitting parallel data, it can be compensated for, so that good parallel data transmission can be realized. can. Furthermore, even if the same transmission path is used, by adopting this compensation method, it is possible to improve the transmission distance and transmission speed.

[Brief explanation of drawings]

Figure 1 is a diagram explaining the principle of the present invention. Figure 2 is a diagram showing an embodiment of the present invention. Figure 3 is a diagram explaining conventional parallel data transmission. Figure 4 is an explanation of setup time and hold time. It is a diagram. In the figure, 11...Signal pattern generation circuit for skew measurement, 12
...Switching control circuit, 13...Driver group, 14...Transmission line, 15...Receiver group, 16...Flip-flop group, 17...OR circuit 18...Latch circuit, 19 ...Clock counter group, 20...Memory, 21...Clock source, 22...Shift register group, 23...Signal pattern detection circuit and skew detection circuit for skew measurement, 24...AND circuit Group, 25... Control circuit, 26... OR circuit, 27... Skew compensation circuit.

Claims (1)

[Claims] A skew measurement signal pattern detection circuit and skew value detection circuit (23
), a control circuit (25) that outputs a control signal such that the delay amount is compensated based on each delay amount detected by the skew measurement signal pattern detection circuit and skew value detection circuit (23); A skew compensation method comprising: a skew compensation circuit (27) that selects and outputs data skew compensated by the control signal from among the parallel outputs, and obtains skew compensated data.