JPH09139730A - Elastic storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain accurate data transmission in all clock timings. SOLUTION: A variable signal delay circuit 14 of the device delays a clock signal (a) to generate a delayed clock signal. The delayed clock signal is given to a latch circuit 13. Furthermore, a phase difference monitor circuit 15 monitors the phase difference between the delayed clock signal ad the clock signal (a) and monitors the phase difference between the delayed clock signal and a clock signal (b) to change a delay in the variable signal delay circuit 14 so that the phase difference is a preset phase difference. Thus, accurate data transmission is conducted without being limited by the phase difference between the clock signal (a) and a data signal B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elastic store, and more particularly to an elastic store used for transmitting digital signals.

[0002]

2. Description of the Related Art Generally, an elastic store is used as a buffer storage device in a multiplexer, and a low-order group signal is written in the elastic store by a write clock and then read by a read clock. And
This read clock is synchronized with the high-order group frame.

In other words, the data signal A is written to the elastic store by the clock signal a, and the data signal B is read from the elastic store by the clock signal b. That is, when the data signal A synchronized with the clock signal a is input to the elastic store, the data signal B is output from the elastic store in synchronization with the clock signal b. At this time, the clock signal a and the clock signal b are frequency-synchronized, and even if there is a phase difference between the clock signal a and the clock signal b, the data signal b has the same content as the data signal a. ing.

Here, referring to FIG. 2, an outline of a conventional elastic store will be described.

The illustrated elastic store has first and second
3 is provided, the clock signal a shown in FIG. 3A is applied to the clock terminal CK of the first latch circuit 11, and the data signal D of the first latch circuit 11 is supplied to the data terminal D of FIG. A data signal A shown in (b) is given.

The data signal A is data 1 to N (see FIG. 3).
(Only the data 1 to 3 are shown in (b)), and the first latch circuit 11 latches the data signal A according to the clock signal a and outputs it as a latch signal at the output terminal Q.
(FIG. 3 (c)). Then, this latch signal is given to the data terminal D of the second latch circuit 12.

Clock terminal CK of the second latch circuit 12
To the clock signal b shown in FIG. 3D via the inverter 12a. That is, the second latch circuit 12
A signal obtained by inverting the clock signal b is applied to the clock terminal CK of. The second latch circuit 12 latches the latch signal according to the clock signal b and outputs it as the data signal B from the output terminal Q (FIG. 3 (e)).

As described above, in the elastic store shown in FIG. 2, the data signal A is written at the timing of the clock signal a and the write signal is read as the data signal B at the timing of the clock signal b. Note that the example shown in FIG. 2 shows a case where the data is 1 bit, and when the number of bits of the data is plural, plural constituent elements shown in FIG. 2 are required.

[0009]

By the way, the elastic store is used when data transmission is performed by absorbing the phase difference between the clock signal a and the clock signal b, and the elastic store between the clock signal a and the clock signal B is used. If there is almost no phase difference between them or if there is jitter in the clock signal a or b, there is a problem that data transmission cannot be performed with the same contents of the data signals A and B.

For example, as described above, the first latch circuit 11 latches the data signal A (FIG. 4 (b)) according to the clock signal a (FIG. 4 (a)) and latches the latched signal (FIG. 4).
However, as shown in FIG. 4D, when the period of the clock signal b is changing due to the jitter, the data 2 of the data signal B is omitted, As a result, data transmission is not performed accurately.

Such a phenomenon similarly occurs when the cycle of the clock signal A changes due to the jitter, and the data cannot be transmitted accurately.

In any case, the conventional elastic store has a problem that it is difficult to perform accurate data transmission at all clock timings.

An object of the present invention is to provide an elastic store capable of accurately transmitting data at all clock timings.

[0014]

According to the present invention, a first data signal is written in response to a first clock signal and a second data signal is written.
In the elastic store for reading out the write signal as the second data signal in accordance with the clock signal, the delay amount variable delay for delaying either the first clock signal or the second clock signal to obtain the delayed clock signal. Means for operating based on the first clock signal
A first intermediate data signal from the first data signal
A second generation unit that operates in response to the delayed clock signal to generate a second intermediate data signal from the first intermediate data signal; and a second operation unit that operates in response to the second clock signal. A third generator for generating the second data signal from a second intermediate data signal, and a phase difference between the delayed clock signal and the first clock signal as a first phase difference and the delay Clock signal and the second
Monitoring means for monitoring the phase difference from the clock signal as the second phase difference and changing the delay amount of the delay means so that the first and second phase differences become the preset phase difference. An elastic store characterized by having:

[0015]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

Referring to FIG. 1, in the illustrated elastic store, the same components as those in the elastic store shown in FIG. 2 are designated by the same reference numerals. The illustrated elastic store has first and second latch circuits 11 and 12.
In addition to the third latch circuit 13, the variable signal delay circuit 14,
And a phase difference monitoring circuit 15. The output terminal Q of the first latch circuit 12 is connected to the data terminal D of the third latch circuit 13, and the output terminal Q of the third latch circuit 13 is connected to the data terminal D of the second latch circuit 12. There is.

Further, the clock signal a is given to the variable signal delay circuit 14, delayed here and given to the phase difference monitoring circuit 15 and the clock terminal CK of the third latch circuit 15 as a delayed clock signal.

The first latch circuit 11 has a clock signal a.
(First clock signal), the data signal A
The (first data signal) is latched and a first latch signal (first intermediate data signal) is output. The third latch circuit 13 operates according to the delayed clock signal, latches the first latch signal, and outputs the second latch signal (second intermediate data signal). The second latch circuit 12 operates according to the clock signal b, latches the second latch signal, and outputs the data signal B (second data signal).

The phase difference monitoring circuit 15 is supplied with the clock signal b in addition to the delayed clock signal.
Monitors the phase difference between the delayed clock signal and the clock signal b and controls the delay amount of the variable signal delay circuit 14 according to the result.

Since the phase difference monitoring circuit 15 controls the delay amount of the variable signal delay circuit 14, the phase difference between the clock signal a and the delayed clock signal can be known based on the delayed clock signal (this The phase difference is called the first phase difference). Further, the phase difference monitoring circuit 15 obtains the phase difference between the delayed clock signal and the clock signal b, and uses this as the second difference.
And the phase difference of. A predetermined phase difference is set in the phase difference monitoring circuit 15 (this phase difference is the minimum phase difference that allows normal data transmission. In other words, the minimum phase difference that does not cause abnormal data transmission. It is determined whether the first and second phase differences are equal to or larger than the set phase difference, and if the first and second phase differences are smaller than the set phase difference, the variable signal delay circuit 14
Change the delay amount of. That is, the delay amount of the variable signal delay circuit 14 is changed so that the first and second phase differences are equal to or larger than the set phase difference.

By changing the delay amount of the variable signal delay circuit 14 in this way, when the phase difference between the clock signal a and the clock signal b is critical, or when the clock cycle is changed by jitter. Also, data transmission can be performed accurately. That is, data transmission can be accurately performed without limitation on the phase difference between the clock signals a and b.

In the above example, the clock signal a is delayed to generate the delayed clock signal, but the clock signal b may be delayed to obtain the delayed clock signal.

[0023]

As described above, according to the present invention, the first or second clock signal is delayed by the delay circuit or the like to obtain the delayed clock signal, and the latch circuit (second The generation unit) is inserted between the latch circuit (first generation unit) that operates at the first clock and the latch circuit (third generation unit) that operates at the second clock, and the delay clock signal Delay circuit so that the phase difference (first phase difference) with the first clock signal and the phase difference (second phase difference) between the delayed clock signal and the second clock signal are equal to or more than a preset phase difference. Since the amount of delay is changed, there is an effect that data can be transmitted accurately without being restricted by the phase difference between the first and second clock signals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an elastic store according to the present invention.

FIG. 2 is a block diagram showing a conventional elastic store.

FIG. 3 is a timing diagram illustrating an operation of the elastic store shown in FIG.

FIG. 4 is a timing diagram illustrating a malfunction of the elastic store shown in FIG.

[Explanation of symbols]

 11, 12, 13 Latch circuit 12a Inverter 14 Variable signal delay circuit 15 Phase difference monitoring circuit

Claims (1)

[Claims] 1. An elastic store in which a first data signal is written in response to a first clock signal and the write signal is read out as a second data signal in response to a second clock signal. Delay means for delaying one of the two clock signals to obtain a delayed clock signal, and a delay amount variable delay means, which operates on the basis of the first clock signal to generate a first intermediate data signal from the first data signal. A first generation unit that generates, a second generation unit that operates according to the delayed clock signal to generate a second intermediate data signal from the first intermediate data signal, and a second generation unit that generates the second intermediate data signal And a third generator that operates in accordance with the second intermediate data signal to generate the second data signal, and a phase difference between the delayed clock signal and the first clock signal as a first phase difference. And monitor the phase difference between the delayed clock signal and the second clock signal as a second phase difference so that the first and second phase differences become preset phase differences. And a monitoring unit for changing the delay amount of the delay unit.