JP3562416B2 - Inter-LSI data transfer system and source synchronous data transfer method used therefor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inter-LSI data transfer system and a source synchronous data transfer method used for the same, and more particularly to a high-speed data transfer between LSIs (large-scale integrated circuits).
[0002]
[Prior art]
As a general data transfer method between LSIs, there is a synchronous transfer method in which a clock generated from the same oscillator (oscillator) is distributed to each LSI and only data is transferred. However, in recent years, it has been required to perform high-speed transfer such that the transfer frequency exceeds 500 MHz.
[0003]
FIG. 8 schematically shows a synchronous transfer method between LSIs. In FIG. 8, the LSIs 5 and 7 are connected by a transmission path 6, and parallel data (n pieces) is exchanged between the LSIs 5 and 7 via the transmission path 6. The LSI 5 includes a flip-flop (hereinafter referred to as F / F) 51 and an output buffer 52, the LSI 7 includes an input buffer 71 and an F / F 72, and the LSIs 5 and 7 are supplied with an LSI external clock.
[0004]
In the LSI 5, when data (n pieces) is output from the internal logic (not shown) to the F / F 51, the F / F 51 operates by inputting an LSI external clock as a transmission side system clock and sends the data to an output buffer 52. To the transmission path 6 via
[0005]
In the LSI 7, when the data (n pieces) transmitted from the transmission path 6 is input via the input buffer 71, the F / F 72 operates by receiving the LSI external clock as a receiving system clock and operates. It is sent to an internal logic not shown.
[0006]
[Problems to be solved by the invention]
In the conventional synchronous transfer method described above, there is no problem if the transfer cycle is short. However, if the transfer cycle is long, clock skew, delay time variation in LSI, delay time variation in media (printed wiring board, cable, connector, etc.), noise And the like become larger than the transfer cycle and become unacceptable, making it impossible to realize.
[0007]
In the synchronous transfer system, even when the wiring is of equal length, no timing guarantee is provided in terms of circuit between the transferred data and the clock of the receiving LSI. For this reason, there is no problem when the transfer cycle is much slower than the delay time. However, when the transfer cycle is faster, the setup / hold time of the F / F of the receiving LSI that receives the transferred data for the first time. May not be satisfied, and accurate transfer may not be performed.
[0008]
That is, at the time of high-speed transfer, adjustment of clock skew between LSIs, and delay time due to transfer are accurately estimated in consideration of the influence of variation and noise, and the setup time and hold time in the F / F on the receiving LSI side are satisfied. There is a problem that transfer cannot be performed without such adjustment.
[0009]
As a high-speed data transfer method used in communication systems, an asynchronous serial transfer method is mainly used. However, since data transfer is not always performed, a transfer start signal must be sent at the start of transfer. I assume it.
[0010]
For this reason, processing such as encoding to serial data before data transfer, detection of a transfer start signal at the time of data reception, decoding of a serial signal, synchronization, and the like are required, and latency (response time) deteriorates. In computer-to-LSI transfer, transfer is always performed except transfer in the input / output system. Since this latency is an important factor in determining performance, the asynchronous serial transfer method cannot be used.
[0011]
Therefore, an object of the present invention is to solve the above-mentioned problems, suppress variations in data delay time during high-speed transfer, and perform an accurate, high-speed, high-response data transfer between LSIs, and use the same. An object of the present invention is to provide a source synchronous data transfer method.
[0012]
[Means for Solving the Problems]
An inter-LSI data transfer system according to the present invention is an inter-LSI data transfer system for transferring data between a large-scale integrated circuit on a sending side and a large-scale integrated circuit on a receiving side, wherein the large-scale integrated circuit on the sending side is provided. And a reference signal for adjusting the timing of the large-scale integrated circuit on the receiving side is supplied to the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side. A transmission path provided between the receiving-side large-scale integrated circuit and for simultaneously transferring a plurality of data and the reference signal and a clock generated from a system clock of the sending-side large-scale integrated circuit ; sampling means for sampling the data transferred via the transmission path clock transferred via the transmission path, before the sampled data And a reference signal and means for synchronizing the system clock of the large-scale integrated circuits at a timing that is generated from the system clock of reading the receiving side of the large scale integrated circuit of the receiving side.
[0013]
The source synchronous data transfer method according to the present invention is a source synchronous data transfer method of an inter-LSI data transfer system for transferring data between a large-scale integrated circuit on a sending side and a large-scale integrated circuit on a receiving side. A reference signal for adjusting the timing of the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side is supplied to the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side, and A plurality of data, the reference signal, and a clock generated from a system clock of the large-scale integrated circuit on the sending side are provided between the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side. receiving said reference signal and said data transferred via the transmission path for transferring after sampling clock transferred via the transmission path And to synchronize the system clock of the large-scale integrated circuits of the sampled the receiving side data is read at a timing that is generated from the system clock of large scale integrated circuits.
[0014]
That is, in the source synchronous data transfer method of the present invention, a clock (hereinafter, referred to as a source clock) is simultaneously transferred from a sending LSI (source) and a plurality of data (n pieces) through the same transmission path, and a receiving LSI ( Receive), the data is sampled with the source clock, and the data is synchronized with the system clock of the receiving LSI.
[0015]
As a result, the source synchronous data transfer method of the present invention makes it possible to suppress variations in the delay time of the transmission path and clock skew, and realize high-speed transfer of parallel data used for transfer between LSIs of a computer.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an inter-LSI data transfer system according to one embodiment of the present invention. In FIG. 1, an inter-LSI data transfer system connects a sending-side LSI (source) 1 and a receiving-side LSI (receive) 2 by transmission paths 3 and 4 (transmission paths 3 and 4 constitute the same transmission path). It is configured.
[0017]
The sending-side LSI 1 includes a flip-flop (hereinafter, referred to as F / F) 11, a source clock generation circuit 12, and output buffers 13 and 14. The receiving LSI 2 includes input buffers 21 and 22, a distribution delay compensation circuit 23, a write address generation circuit 24, a read address generation circuit 25, a FIFO (First-In First-Out) circuit 26, and an F / F 27. It is comprised including.
[0018]
A plurality of data (n pieces) and a clock (hereinafter, referred to as a source clock) are simultaneously transferred from the sending LSI 1 and on the same transmission paths 3 and 4, and the receiving LSI 2 samples the data with the source clock and then receives the data. By synchronizing with the system clock of the side LSI 2, variations in the delay time of the transmission path and clock skew can be suppressed, and high-speed transfer of parallel data used for transfer between LSIs of a computer can be realized.
[0019]
FIG. 2 is a circuit diagram showing a configuration of the source clock generation circuit 12 of FIG. In FIG. 2, a source clock generation circuit 12 includes F / Fs 12a, 12b, 12g, an AND circuit 12c, NAND circuits 12d, 12e, and a selector 12f. ) A signal and a sending side system clock are input to generate a source clock.
[0020]
FIG. 3 is a circuit diagram showing a configuration of the write address generation circuit 24 of FIG. In FIG. 3, a write address generation circuit 24 includes F / Fs 24a and 24b, and receives a reset signal and an output of the input buffer 22 to generate write addresses a to d.
[0021]
FIG. 4 is a circuit diagram showing a configuration of the read address generation circuit 25 of FIG. In FIG. 4, a read address generation circuit 25 includes shift registers F / Fs 25a to 25d, and generates read addresses A to D by inputting a reset signal, a definer signal, and a receiving system clock.
[0022]
FIG. 5 is a circuit diagram showing a configuration of the FIFO circuit 26 of FIG. In FIG. 5, a FIFO circuit 26 includes F / Fs 26a to 26d, selectors 26e to 26h, and 4to1 selectors 26i to 26l. Output data to be output.
[0023]
An inter-LSI data transfer system according to an embodiment of the present invention will be described with reference to FIGS. In the above circuit example, apparently, synchronous transfer is performed for four clock cycles. The data and the source clock are simultaneously transferred from the sending LSI 1 to the receiving LSI 2 via the same transmission paths 3 and 4. In order to perform sampling at an effective point of the data signal waveform, the source clock is sent with a shift of half a cycle with respect to the data.
[0024]
The source clock is generated by the F / F 12g in the source clock generation circuit 12 by dividing the frequency of the source clock by 1/2 at the opposite phase. Further, in order to match the timings of the sending side LSI1 and the receiving side LSI2, a definer signal is distributed to the sending side LSI1 and the receiving side LSI2 from outside the LSI. The definer signal is a signal having a frequency of １ ／ of the system clock in which “HI”: “LOW” = 1: 3.
[0025]
The data transferred to the receiving LSI 2 passes through the distribution delay compensation circuit 23, is sampled by the transferred source clock, and stored in the FIFO circuit 26. The FIFO circuit 26 is a data holding circuit that holds data for a certain period and outputs the data in the order in which the data is stored.
[0026]
Since the source clock is distributed to the FIFO circuit 26 and the write address generation circuit 24 that receive each data, the delay is larger than that of the data. This delay difference reduces the margin between the data and the source clock for sampling the data. Therefore, the delay difference is compensated for by a distribution delay compensating circuit 23 that corrects a delay equivalent to the source clock distribution delay on the data side.
[0027]
This embodiment shows a case where the FIFO circuit 26 has four stages per data bit. In this case, the FIFO circuit 26 holds data for four system clock cycles.
[0028]
A write address generation circuit 24 that generates write addresses a to d from a source clock to determine the order of writing to the FIFO circuit 26, and a read address that generates read addresses A to D from a definer signal to determine the order of reading And a generation circuit 25. The write address is synchronized with the source clock, and the read address is synchronized with the receiving clock.
[0029]
In addition to these components, the sending LSI 1 includes a data F / F 11 and output buffers 13 and 14 in the present invention. The receiving LSI 2 has input buffers 21 and 22 and an F / F 27 that receives the transmitted data via the FIFO circuit 26 at the clock of the receiving LIS2.
[0030]
FIG. 6 is a timing chart showing the operation of the source clock generation circuit 12 in FIG. 1, and FIG. 7 is a timing chart showing the operation of the receiving LSI 2 in FIG. The operation of the embodiment of the present invention will be described with reference to FIGS.
[0031]
First, the operation of the source clock generation circuit 12 in the sending side LSI 1 will be described. As shown in FIG. 6, the definer signal is a signal having a frequency of １ ／ of the system clock in which “HI”: “LOW” = 1: 3.
[0032]
As for the source clock, after the output of the F / F 12b receiving the reset signal at the sending side system clock is released from the reset state ("LOW" → "HI"), the output of the F / F 12a receiving the definer signal at the sending side system clock is "HI" for the first time. Is generated by dividing the frequency of the next system clock from the falling edge by 1/2.
[0033]
That is, the transmission start timing of the source clock is defined by the definer signal and the reset signal. The selector 12f at the preceding stage of the F / F 12g selects the lower side when the output of the NAND circuit 12d is "LOW", and selects the upper side when the output of the NAND circuit 12d is "HI".
[0034]
Next, the operation of the receiving LSI 2 will be described. After the data [FIG. 7 (a)] and the source clock [FIG. 7 (b)] are transferred from the sending LSI 1 to the receiving LSI 2 via the completely same transmission paths 3 and 4, the relationship between the data [FIG. c)] and the source clock [FIG. 7 (d)].
[0035]
This source clock [FIG. 7 (d)] is input to the clock input of the F / F 24a that operates on the positive edge and the F / F 24b that operates on the reverse edge of the write address generation circuit 24. These F / Fs 24a and 24b connect a negative output to an input and constitute a 1/2 frequency dividing circuit. The source clock is a system clock shifted by a half cycle and the frequency is a half signal, so the positive and negative outputs of the F / Fs 24a and 24b are signals of a quarter frequency of the system clock shifted by a half cycle with respect to the data input. It becomes.
[0036]
These signals are shifted by one period as shown in FIGS. 7 (e) to 7 (h). The signals shown in FIGS. 7E to 7H are referred to as write address signals. However, it is necessary to initialize the F / F 24a and the F / F 24b constituting the write address generation circuit 24 before the operation.
[0037]
When these select signals are in the "HI" state, the selectors 26e to 26h preceding the F / Fs 26a to 26d constituting the FIFO circuit 26 select the lower side. In the "LOW" state, the selectors 26e to 26h select the upper side, that is, hold the data.
[0038]
Unlike the F / Fs 26a and 26c, the F / Fs 26b and 26d constituting the FIFO circuit 26 perform the data fetch operation at the falling edge of the clock. Therefore, the data [FIG. 7 (c)] is stored while being shifted by one cycle, such as F / F26a → F / F26b → F / F26c → F / F26d → F / F26a →. The data is held by the F / Fs 26a to 26d for four cycles. Therefore, the outputs of the F / Fs 26a to 26d are as shown in FIGS.
[0039]
Further, the definer signal [FIG. 7 (n)] is synchronized with the receiving side system clock [FIG. 7 (m)], input to the shift registers F / F 25a to 25d constituting the read address generation circuit 25, and read address A To D [FIG. 7 (o) to (r)]. However, in order to avoid a multiselect in which the output of the FIFO circuit 26 causes a bus fight, it is necessary to initialize the shift registers F / Fs 25a to 25d before the operation.
[0040]
The read addresses A to D are input to the select signals of the 4to1 selectors 26i to 26l that receive the outputs of the F / Fs 26a to 26d. Since the path is activated in the “HI” state, the output of the FIFO circuit 26 is as shown in FIG.
[0041]
As described above, the data input to the FIFO circuit 26 is output in the input order. As a result of sampling this output with the receiving system clock [FIG. 7 (m)], a data signal [FIG. 7 (t)] synchronized with the receiving clock is sent to the internal logic (not shown). However, in this embodiment, it is necessary to adjust the refiner signal distributed from the outside so as not to be in a metastable state with the sending system clock and the receiving system clock. Further, the definer signal and the LSI external clock need to be supplied from the same oscillator.
[0042]
In the transfer method according to the present embodiment, the delay variation from the F / F of the sending LSI 1 to the output pin and the delay variation from the input pin to the F / F (FIFO) of the receiving LSI 2 can be regarded as a delay time difference in the same LSI. Since the data and the source clock are transferred via the same circuit and the same medium (package, cable, etc.), it is possible to suppress the variation in the delay time between the data and the source clock.
[0043]
Therefore, in this embodiment, accurate and high-speed data transfer can be performed without adjusting the clock skew or the like outside the LSI. Further, since it appears as a synchronous transfer with a multi-clock cycle, the designer does not need to be conscious of a special transfer method, and can consider it as an extension of the conventional synchronous transfer method.
[0044]
Furthermore, unlike the asynchronous serial transfer method in the present embodiment, there is no need to perform encoding and decoding on serial data, so that responsiveness (latency) is improved.
[0045]
In the present embodiment, the number of data is n for one source clock. However, the number of data is arbitrary within a range where the variation between the source clock and the data does not exceed one clock cycle. Further, the number of stages of the FIFO circuit 26 is also four, but may be two or eight, and these can be operated with an arbitrary number of stages.
[0046]
Further, in this circuit configuration, apparently, synchronous transfer with a period of 4 clocks may be apparent, but it may be 3 clocks or 5 clocks, and they can be operated at an arbitrary clock period, and can be changed according to the transfer time between LSIs. It is possible. However, along with this, it is necessary to change the number of stages of the FIFO, the circuit configuration of the read address generation circuit and the write address generation circuit, and the signal waveform of the definer signal to a circuit that conforms thereto.
[0047]
The source clock does not need to be generated by dividing the frequency by で with the opposite phase of the sending clock, and if it can be accurately sampled by the FIFO circuit 26 of the receiving LSI 2, there is no need to send the source clock shifted by a half cycle. If the variation between the source clock and the data after distribution in the receiving LSI 2 is small, the distribution delay compensation circuit 23 may be omitted.
[0048]
The write address generation circuit 24 and the read address generation circuit 25 are not limited to the circuit configuration shown in FIGS. 3 and 4, and may use a counter, for example. If a delay occurs, logic may be inserted between the FIFO circuit 26 and the F / F 27.
[0049]
【The invention's effect】
As described above, according to the present invention, in an inter-LSI data transfer system for transferring data between a large-scale integrated circuit on the sending side and a large-scale integrated circuit on the receiving side, the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side are transferred. Data that is provided between the large-scale integrated circuit on the side and that is transferred via a transmission path for simultaneously transferring a plurality of data and a clock is sampled by a clock that is transferred via the transmission path. Later, by synchronizing the sampled data with the system clock of the large-scale integrated circuit on the receiving side, it is possible to suppress variations in data delay time during high-speed transfer, and perform accurate, high-speed, high-response data transfer. There is an effect that can be.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an inter-LSI data transfer system according to one embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a source clock generation circuit of FIG.
FIG. 3 is a circuit diagram showing a configuration of a write address generation circuit of FIG. 1;
FIG. 4 is a circuit diagram showing a configuration of a read address generation circuit of FIG. 1;
FIG. 5 is a circuit diagram showing a configuration of the FIFO circuit of FIG. 1;
FIG. 6 is a timing chart showing an operation of the source clock generation circuit of FIG. 1;
FIG. 7 is a timing chart showing the operation of the receiving LSI of FIG. 1;
FIG. 8 is a block diagram showing a configuration of a conventional inter-LSI data transfer system.
[Explanation of symbols]
1 sending side LSI
2 Receiver LSI
3, 4 transmission paths 11, 27, 12a,
12b, 12g, 24a,
24b, 26a to 26d Flip-flop 12 Source clock generation circuit 12c AND circuit 12d, 12e NAND circuit 12f, 26e to 26h Selector 13, 14 Output buffer 21, 22 Input buffer 23 Distribution delay compensation circuit 24 Write address generation circuit 25 Read address generation Circuits 25a to 25d Shift register F / F
26 FIFO circuits 26i to 26l 4to1 selector

Claims (10)

An inter-LSI data transfer system for transferring data between a large-scale integrated circuit on a sending side and a large-scale integrated circuit on a receiving side, comprising: the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side; The reference signal that adjusts the timing of the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side is supplied to the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the sending side. A transmission path provided between the transmission paths for simultaneously transferring a plurality of data and the reference signal and a clock generated from a system clock of the large-scale integrated circuit on the transmission side; and a transmission path via the transmission path. sampling means for sampling the data clock transferred via the transmission path, the sampled data of large-scale integrated circuits of the reference signal and the receiving side LSI data transfer system characterized by a means for synchronizing the system clock of a large scale integrated circuit for reading the receiving side at a timing that is generated from the system clock. 2. The data transfer between LSIs according to claim 1, wherein a generating means for generating a clock transferred to the large scale integrated circuit on the receiving side via the transmission path is included in the large scale integrated circuit on the sending side. system. 3. The receiving large-scale integrated circuit according to claim 1, wherein the receiving large-scale integrated circuit includes a distribution delay compensating circuit that applies a delay equivalent to a distribution delay of the clock in the receiving large-scale integrated circuit to the data. A data transfer system between LSIs as described above. 4. The LSI according to claim 1, wherein the number of the data is set to an arbitrary value within a range in which a variation between the clock and the data does not exceed one clock cycle. 5. Data transfer system. The data transfer between the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side can be operated at an arbitrary clock cycle. Data transfer system between LSIs. A source synchronous data transfer method of an inter-LSI data transfer system for transferring data between a large-scale integrated circuit on a sending side and a large-scale integrated circuit on a receiving side, wherein the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side are transferred. A reference signal for adjusting the timing with the large-scale integrated circuit on the sending side is supplied to the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side, and the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side are supplied. And a plurality of data and a reference signal and a clock generated from a system clock of the sending-side large-scale integrated circuit, which are provided between the large-scale integrated circuit and the transmission-side large-scale integrated circuit. the data generated from the system clock of large-scale integrated circuits of the reference signal and the received side after sampling clock transferred via the transmission path Source synchronous data transfer system, characterized in that synchronizing the system clock of the large-scale integrated circuits of the sampled the receiving side data is read at the timing. 7. The source synchronous data transfer according to claim 6, wherein the clock transferred to the large scale integrated circuit on the receiving side via the transmission path is generated by the large scale integrated circuit on the sending side. method. 8. The source synchronous data transfer system according to claim 6, wherein a delay equivalent to a distribution delay of the clock in the large-scale integrated circuit on the receiving side is applied to the data. 9. The source synchronization according to claim 6, wherein the number of the data can be set to an arbitrary value within a range in which a variation between the clock and the data does not exceed one clock cycle. Eggplant data transfer method. 10. The data transfer between the large-scale integrated circuit on the sending side and the large-scale integrated circuit on the receiving side is operable at an arbitrary clock cycle. Source synchronous data transfer method.

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