JP3312647B2 - Flip-flop circuit with asynchronous set / reset - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit used in a digital circuit, and more particularly to a flip-flop with an asynchronous set / reset.

[0002]

2. Description of the Related Art Some flip-flop circuits used in digital circuits have a set function and a reset function. The set function and the reset function also have a synchronous type that synchronizes with the clock and a synchronous type that does not synchronize with the clock. There is an asynchronous type.

[0003] As a prior art related to the present invention,
There is an "edge-triggered set / reset flip-flop" described in Japanese Utility Model Laid-Open No. 3-94829 and a "control signal conversion device and control signal conversion method" described in Japanese Patent Application Laid-Open No. 8-137635.

[0004]

When designing a gate array or a cell-based ASIC, a flip-flop block (FIG. 3) holding both asynchronous set and asynchronous reset functions is prepared as usable functional blocks. If not, and the design specification requires a flip-flop circuit with asynchronous set / reset, the designer is forced to change the design specification.

[0005] Even if a flip-flop block with an asynchronous set or a flip-flop block with an asynchronous reset, which is usually prepared, is in a library, only one of these flip-flop functions is selected to perform logical design. It is inevitable that the design specifications will be changed accordingly.

As a special case, as shown in FIG. 4, a pseudo-flip-flop circuit with asynchronous set / reset in which a flip-flop block with asynchronous reset (set) is combined with a synchronous set (reset) circuit is used. In some cases, changes in design specifications are inevitable.

An object of the present invention is to provide a flip-flop with an asynchronous set / reset using a flip-flop with an asynchronous set and a flip-flop with an asynchronous reset.

[0008]

SUMMARY OF THE INVENTION A flip-flop circuit with an asynchronous set / reset according to the present invention is a flip-flop circuit with an asynchronous set, and a flip-flop circuit with an asynchronous reset sharing the clock and data with the flip-flop circuit with the asynchronous set. And outputs the output of the flip-flop circuit with the asynchronous set to a final output until the reset signal input to the flip-flop circuit with the asynchronous reset is input after the set signal input to the flip-flop circuit with the asynchronous set is input. And a means for selecting an output of the flip-flop circuit with the asynchronous reset as a final output until the set signal is input after the reset signal is input.

The flip-flop circuit with an asynchronous set / reset according to the present invention includes a flip-flop circuit with an asynchronous set, a flip-flop circuit with an asynchronous reset sharing the clock and data with the flip-flop circuit with the asynchronous set, and A set signal input to the flip-flop circuit with a set and a reset signal input to the flip-flop circuit with an asynchronous reset are input, and from when the set signal is activated until the reset signal is activated. A set signal detection and holding circuit that outputs a first selection signal that is only active, and that receives the set signal and the reset signal, from when the reset signal becomes active until the set signal becomes active. Active only for a while A reset signal detection and holding circuit that outputs a second selection signal; and an output of the flip-flop circuit with an asynchronous set when the first selection signal is active, wherein the second selection signal is active. Selection means for occasionally selecting the output of the flip-flop circuit with asynchronous reset and outputting it as the final output.

Further, the flip-flop circuit with an asynchronous set / reset according to the present invention includes the asynchronous set / reset.
In the flip-flop circuit with reset, the set signal detection and holding circuit includes an inverted output exclusive OR circuit for inputting the set signal and the reset signal, and an output of the inverted output exclusive OR circuit to one input. A two-input AND circuit, a delay element for inverting the set signal and a delay equal to or longer than a propagation delay time obtained by combining the exclusive-OR circuit and the two-input AND circuit, An OR circuit that inputs an output and an output of the delay element, and outputs the output as an output of the set signal detection and holding circuit, and supplies the output to the two-input AND circuit. An inverting output exclusive OR circuit for inputting the set signal and the reset signal, a two-input AND circuit having an output of the inverting output exclusive OR circuit as one input, A delay element for delaying a reset signal by a time equal to or longer than a propagation delay time obtained by combining the inverted output exclusive OR circuit and the two-input AND circuit, and an output of the two-input AND circuit and an output of the delay element. And an OR circuit for inputting and outputting an output of the reset signal detection and holding circuit and supplying the output to the two-input AND circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A flip-flop circuit having both functions of an asynchronous set and an asynchronous reset is replaced with a flip-flop block with an asynchronous set and a flip-flop block with an asynchronous reset which are usually prepared. The feature is that by realizing it, changes in design specifications can be avoided.

FIG. 1 is a block diagram showing an asynchronous set according to this embodiment.
This is a configuration circuit for realizing a flip-flop with reset.

Referring to FIG. 1, the flip-flop with asynchronous set / reset according to the present embodiment includes a flip-flop with asynchronous set 3, a set signal detection and holding circuit 5, a flip-flop with asynchronous reset 1 and a reset signal detection and holding circuit 4, And an output data selection circuit 6.

When the set signal 9 becomes active, the set signal detecting and holding circuit 5 selects the operation of the flip-flop 3 with the asynchronous set as the output data 13 until the reset signal 10 becomes active next time. Occurs. At this time, the reset signal detection and holding circuit 4 generates the select signal 12 which does not select the operation of the flip-flop 1 with the asynchronous reset as the output data 13.

When the reset signal 10 becomes active, the reset signal detection and holding circuit 4 selects the operation of the flip-flop with asynchronous reset 1 as the output data 13 until the next time the set signal 9 becomes active. Generate signal 12. At this time, the set signal detection and holding circuit 5 operates the flip-flop 3 with the asynchronous set.
Is not selected as the output data 13. FIG. 2 shows a time chart of the configuration circuit of FIG.

When the reset signal 10 becomes active (in this case, "1"), the reset signal detection and holding circuit 4
Generates a select signal 12 for selecting the operation of the flip-flop 1 with asynchronous reset as output data 13. As a result, flip-flop 1 with asynchronous reset
Reset level "0" level controls output data 13. Next, when the reset signal 10 is released (in this case, “0”), the reset signal detection holding circuit 4 outputs the operation of the flip-flop 1 with the asynchronous reset to the output data 13.
Select signal 12 is selected. The principle is that the exclusive OR gate 22 at the first stage recognizes the release of the reset signal, and the select signal is maintained between the AND gate 24 at the second stage and the OR gate 26 at the third stage. It has a mechanism. The exclusive OR gate 22 in the first stage and the logical product gate 24 in the second stage are set so that the released reset signal 10 (in this case, "0") does not destroy the select signal 12 to be maintained. In order to compensate for a propagation delay time equal to or more than
It is necessary to prepare. As a result, until the next time the set signal 9 becomes active (in this case, “1”), the operation of the flip-flop 1 with the asynchronous reset causes the output data 1
Continue to dominate 3. When the set signal 9 subsequently becomes inactive, the output of the exclusive OR gate 22 becomes "1", but the output of the OR circuit 26 which is one input of the AND gate 24 is "0". , The storage circuit constituted by the AND gate 24 and the OR gate 26 is not set.

Next, when the set signal 9 becomes active (in this case, "1"), the set signal detection and holding circuit 5
Generates a select signal 11 for selecting the operation of the flip-flop 3 with asynchronous set as output data. As a result, the set state value “1” level of the flip-flop 3 with the asynchronous set controls the output data 13. Next, when the set signal 9 is released (in this case, “0”), the set signal detection and holding circuit 5 maintains the select signal 11 for selecting the operation of the flip-flop 3 with the asynchronous set as the output data 13. The principle is that the exclusive OR gate 21 at the first stage recognizes the release of the set signal,
Second stage AND gate 23 and third stage OR gate 25
And the select signal 11 is maintained. Note that the released set signal 9 (in this case, "
0 ") to prevent the select signal 11 to be maintained from being destroyed, so that the exclusive OR gates 21 and 2 in the first stage are not destroyed.
It is necessary to prepare the delay line 7 in order to compensate for a propagation delay time equal to or longer than the propagation delay time of the AND gate 23 of the stage. As a result, until the next reset signal 10 becomes active (in this case, “1”), the operation of the flip-flop 3 with the asynchronous set continues to control the output data 13.

Although the present embodiment has been described by taking a D-type flip-flop as an example, the flip-flop type is not limited to this, and can be applied to, for example, a JK type flip-flop.

[0019]

As described above, according to the present invention, when designing a gate array or a cell-based ASIC, a flip-flop block (FIG. 3) having both asynchronous set and asynchronous reset functions is used. Even if it is not provided as a possible functional block, the designer usually configures the flip-flop with asynchronous set / reset using the flip-flop block with asynchronous set and the flip-flop block with asynchronous reset provided. be able to. Therefore, it is possible to realize a logical design that is faithful to the design specifications, and to avoid unreasonable changes in the design specifications.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a flip-flop circuit with an asynchronous set / reset according to the present invention.

FIG. 2 is a timing chart of the operation of the flip-flop circuit with asynchronous set / reset shown in FIG. 3;

FIG. 3 is a functional block diagram of a flip-flop circuit with an asynchronous set / reset.

FIG. 4 is a circuit diagram of a flip-flop circuit with a synchronous set / asynchronous reset according to a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 flip-flop circuit with asynchronous reset 3 flip-flop circuit with asynchronous set 4 reset signal detection and holding circuit 5 set signal detection and holding circuit 6 selection circuit 7 delay line

Claims (3)

(57) [Claims] A flip-flop circuit with an asynchronous set; a flip-flop circuit with an asynchronous reset sharing the clock and data with the flip-flop circuit with the asynchronous set; and a set signal input to the flip-flop circuit with the asynchronous set. Means for selecting an output of the flip-flop circuit with an asynchronous set as a final output until a reset signal input to the flip-flop circuit with an asynchronous reset is input, and the set signal after the reset signal is input. Means for selecting an output of the flip-flop circuit with an asynchronous reset as a final output until a signal is input to the flip-flop circuit with an asynchronous set / reset. 2. A flip-flop circuit with an asynchronous set, a flip-flop circuit with an asynchronous reset that shares clock and data with the flip-flop circuit with the asynchronous set, a set signal input to the flip-flop circuit with the asynchronous set, A reset signal that is input to a flip-flop circuit with an asynchronous reset, and outputs a first selection signal that is active only from when the set signal is activated until the reset signal is activated. A signal detection and holding circuit, a second circuit which receives the set signal and the reset signal, and is active only after the reset signal is activated until the set signal is activated.
A reset signal detection and holding circuit that outputs a selection signal of the following: when the first selection signal is active, selects an output of the flip-flop circuit with an asynchronous set, and when the second selection signal is active Selecting means for selecting an output of the flip-flop circuit with an asynchronous reset and outputting the selected output as a final output, wherein the flip-flop circuit with an asynchronous set / reset is provided. 3. The flip-flop circuit with an asynchronous set / reset according to claim 2, wherein the set signal detection and holding circuit includes an inverted output exclusive OR circuit that inputs the set signal and the reset signal; A two-input AND circuit having an output of the inverted output exclusive OR circuit as one input, and a time equal to or longer than a propagation delay time obtained by combining the set signal with the inverted output exclusive OR circuit and the two-input AND circuit A delay element for delaying
An OR circuit that inputs an output of an input AND circuit and an output of the delay element, outputs an output of the set signal detection holding circuit, and supplies the output to the two-input AND circuit. A holding circuit configured to input the set signal and the reset signal; an inverting output exclusive OR circuit; a two-input AND circuit having an output of the inverting output exclusive OR circuit as one input; A delay element for delaying a time equal to or longer than a propagation delay time obtained by combining the inverted output exclusive OR circuit and the two-input AND circuit, and an output of the two-input AND circuit and an output of the delay element. A flip-flop circuit with an asynchronous set / reset, the output of which is an output of the reset signal detection and holding circuit, and an OR circuit which supplies the output to the two-input AND circuit. .