RU1827054C - Frame synchronizer - Google Patents

Abstract

The invention relates to automation, computer engineering, technology for transmitting discrete information and can be used in digital communication systems with cyclic synchronization. The goal is to increase the accuracy of cyclic synchronization and noise immunity. The cyclic synchronization device comprises a trigger 1 for storing a positive mismatch, a trigger 2 for storing a negative mismatch, the first and second AND elements 34. an OR element 5, a pulse counter-divider 6, a positive matching unit 7, which contains a trigger 8, an And 9 element, a block A negative mismatch selection 10, comprising a trigger 11, an AND element 12, a pulse subtracting unit 13, a pulse adding unit 14, a clock distributor 15, a high-frequency generator 16.2 or.

Description

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The invention relates to automation, computer engineering, technology for transmitting discrete information and can be used in digital communication systems with cyclic synchronization.

The purpose of the invention is to improve the accuracy of cyclic synchronization and noise immunity.

Figure 1 presents the Structural electrical circuit of a cyclic synchronization device; Fig. 2 is a timing diagram of the exchange of information, where a is option I (ahead of the information signal of subscriber 2); b - option II (subscriber information signal lag 2), GI - pulse generator.

The cyclic synchronization device contains a trigger 1 for storing a positive mismatch, a trigger 2 for storing a negative mismatch, the first and second elements AND 3, 4, an OR element 5, a pulse divider counter b, a positive mismatch selection block 7 containing a trigger 8, an element And 9, block 10, select the negative mismatch, containing the trigger 11. element And 12, block

13 subtracting pulses, pulse adding unit 14, clock distributor 15, high-frequency generator 16.

The cyclic synchronization device operates as follows.

At the same time, consider the operation of the device in two modes: positive and negative phase mismatch of pulses T1 and T2.

Positive Mismatch Mode (Fig. 2a).

The SI1-SI4 pulses provide triggering of trigger 8 for a positive mismatch - the And 9 element opens and if a pulse arrives at the signal input of the device (C), then it passed the And 9 element, set 1 trigger 1 to memorize the positive mismatch, which the queue will open the block

14 of adding pulses, element And 4. In this case, synchronous pulses will begin to arrive at the control input of the addition of the clock distributor 15 from the output of the pulse adding unit 14 until the pulse counter-divider b generates an overflow signal that resets the trigger 1 for memorizing the positive mismatch O.

Negative mismatch mode (Fig. 26).

Pulses SI5-SI8 trigger trigger 11 to detect negative mismatch opens element And 12 and if this

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time, a pulse arrives at the signal input of the device (C), then it passes through the And 12 element, set the trigger 2 to store the negative mismatch in G, which in turn will open the pulse subtraction unit 13 and the And 3 element. At the same time, the subtraction control input (- ) the clock distributor 15 from the output of the pulse subtraction unit 13, synchronous pulses will begin to arrive until then. until the pulse counter-divider 6 generates an overflow signal that will reset the negative mismatch trigger 2 to state O.

Claims (1)

SUMMARY OF THE INVENTION A cyclic synchronization device comprising a high-frequency generator, a clock distributor, a pulse subtraction unit, a pulse addition unit, a positive misregistration selection unit and a negative misregistration selection unit, characterized in that, in order to improve the accuracy of the cyclic synchronization and noise immunity, a positive misregistration memory trigger is introduced , a trigger for memorizing negative mismatch, a counter-divisor of pulses, the first and second elements of And OR element, the output of which is connected to the input of the pulse divider counter, while the input of the positive mismatch select block is connected to the input of the negative mismatch select block and is the signal input of the device, and the outputs of the positive mismatch select block and the negative mismatch select block are connected to the unit setup inputs respectively, a trigger for memorizing a positive misalignment and a trigger for memorizing a negative misalignment, to the zero inputs of which the transfer output of the counter-pulse divider is switched on, and the single output of the positive mismatch trigger is connected to the first input of the second AND element and the first input of the pulse adding unit, the output of which is connected to the control input of the addition of the clock distributor, to the control input of which the output of the high-frequency generator is connected, and the single output of the negative mismatch trigger is connected to the first input of the first AND element and the first input of the pulse subtraction unit ow, the output of which is connected to the control input of the subtractor of the clock distributor, while the second input of the pulse adding unit is connected to the second input of the first element And is the first clock input of the device, the second clock input of which is the second input of the calculation unit of the subscriber df with Line with $ si iNo. with subscriber (sishrodod) ($ one & m df fct / wpoSod) Ct C) ff Guy III cg Ycmoi / wfioza zone si Tanya, connected to the second input of the second AND element, the output of which and the output of the first AND element are connected to the inputs of the OR element. Cf M 1 1 C1 I AM