SU1411975A1 - Frequency to number converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in communication systems for computing machines with control objects, for processing signals from frequency sensors. The purpose of the invention is to expand the functionality by converting the rate of change of a period into a code. To do this, a frequency converter with a code containing a clock generator, a frequency divider, a pulse distributor, a three-stage buckle element, two synchronizers, a reversible counter, and switches, two delay elements, three synchronizers, two reversible counters, and two commutators are introduced. continuously convert to the code frequency, the period of the rate of change of the period of the input signal. 1 il. (L

Description

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The invention relates to the field t of pulsed technology and can be used to communicate computational

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From it to the bus. The period is taken using the switch 15.

Continuous conversion to code

i machines with control objects, for the rate of change of the period of realization of signals from frequency sensors.

The purpose of the invention is to expand the functionality of T1 by converting the rate of change of a period to a code.

The drawing shows a block diagram of the converter.

The converter contains a clock

is as follows.

For this, two pulse sequences are formed: the input one and its delayed value on the delay element} 0, and using delay elements 4 and 5 and the reversible counter 13, the difference of the periods of these pulse sequences is converted into a code. Difference

oscillator 1, divider | z 2 frequencies, 15 periods of the input frequency and its predeterminer 3 pulses, the first, second and third elements 4-6 delay, the first, second, third, fourth and fifth synchronizers 7-11, the first, , second and third reversible counters 20 12-14, first, second and third com-: mutators 15-17 ..

The converter works as follows

At the initial moment of operation over bus 25, the reset is performed to reset the counters 12-14 to the zero state, and the duration of the reset signal must be greater than the maximum delay time in elements 4-6 for their complete cleaning. After the termination of the signal Reset, a simultaneous conversion into a code of the frequency, period, and rate of change of the period begins.

The frequency conversion into a code is carried out as follows.

The input frequency from the input bus through the synchronizer 10 is fed to the summing input of the reverse counting value due to the fact that the input frequency is fed to the clock input of the delay element 4 and the same frequency delayed by the delay element 6 is fed to the clock input element 5 delays .. The reference frequency from frequency divider 2 is fed to the inputs of elements 4 and 5, the delays from whose outputs this frequency through synchronizers 8 and 9 is fed to the summing and subtracting inputs of the reversing counter 13 respectively but. A code proportional to the difference in the input frequency, frequency, and delayed values is formed by the delay of the delay element 4 controlled by the input frequency, and the delay time of the delay element 5 is controlled by the delayed value of the input frequency. Thus, on the counter 13, the input frequency period is continuously subtracted from the frequency period delayed by

Chika 14 and the same frequency, passing through an ele-ment to element 6 of the delay, i.e. in the code Nement 6 delay and the synchronizer 11, is fed to the subtracting input of the reversible counter 14. The readings of the counter 14 track the value of the frequency in the code. The code from counter 14 is removed j per bus Frequency using the switch 1 7.

The conversion of a period into a code is carried out as follows.

The input frequency is fed to the clock input element 4 of the delay, and the reference frequency from the splitter 2 frequency is fed through the synchronizer 7 to the summing reversing input

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the rate of change of the period of the input frequency is continuously monitored — it is determined how much the period of the input frequency has changed over the time determined by delay element 6. In this case, since the counter code 13 is additional, depending on whether the period is increasing or decreasing, either a positive or a negative code is generated. The readings from counter 13 are taken using the switch 16. The switches 15-17 are controlled from the third output of the distributor 3.

counter 12 directly and to its control: synchronizers 7-11 BS input reading - via element 4 acquires the first and second shutter speeds and synchronizer 8. Spread distributor 3 counter. Frequency also- 12 HenpepbtBHO monitors the value of the input frequency, and indications.

This generator 1 must be chosen so that the frequency of the pulses

is as follows.

For this, two pulse sequences are formed: the input and its delayed value on the delay element, and with the help of delay elements 4 and 5 and the reversible counter 13, the period difference of these pulse sequences is converted into a code. Difference

This value is due to the fact that the input frequency arrives at the clock input of delay element 4 and the same frequency, delayed by delay element 6, arrives at the clock input of delay element 5. The reference frequency from frequency divider 2 goes to the inputs of elements 4 and 5, the delays from the outputs of which this frequency through the synchronizers 8 and 9 is fed to the summing and subtracting inputs of the reversible counter 13, respectively. A code proportional to the difference in the input frequency, frequency, and delayed values is formed by the delay of the delay element 4 controlled by the input frequency, and the delay time of the delay element 5 is controlled by the delayed value of the input frequency. Thus, on the counter 13, the input frequency period is continuously subtracted from the frequency period delayed by

j

0

the rate of change of the period of the input frequency is continuously monitored — it is determined how much the period of the input frequency has changed over the time determined by delay element 6. In this case, since the counter code 13 is additional, depending on whether the period is increasing or decreasing, either a positive or a negative code is generated. The readings from counter 13 are taken using the switch 16. The switches 15-17 are controlled from the third output of the distributor 3.

Most important from the first and second outputs of the distributor 3. The frequency is also

This generator 1 must be chosen so that the frequency of the pulses

3

at the outputs of the distributor 3 was higher than the maximum value of the input frequency in order not to introduce significant time shifts of the pulses at the inputs of the reversible counters 12-14, the division factor of the divider 2 frequency must be chosen such that the frequencies on the elements 4 are always exceeded and 5 delays over the frequencies at the inputs of these delay lines.

Thus, a new function is implemented in the converter — a continuous conversion to a code for the rate of change of the period simultaneously with the conversion to the code of the frequency itself and its period. The same delay lines, the most capacious in terms of equipment, are used. The advantage of the converter is also that the code for the rate of change of the period is generated with a sign indicating that the period of the input frequency increases or decreases.

Claims (1)

Invention Formula A frequency converter into a code containing a clock generator connected to the inputs of the frequency splitter and the pulse distributor, the first and second outputs of which are connected to the first inputs of the first and second synchronizers, respectively, and the third output to the control input of the first switch, the second input of the first synchronizer combined with the input of the first delay element, the output of which is connected to the second input of the second synchronizer, the output of the first synchronizer is connected to the summing input of the first reversible counter, the input of which is connected to the output of the second synchronizer, the outputs of the first reversible counter are connected to the corresponding inputs of the first switch, the outputs of which are 75 output bus Period characterized in that, in order to extend the functionality, it introduced the second and third delay elements, the third, fourth and fifth synchronizers, the second / third and third reversible counters and the second and third switches, and Frequency splitter output is connected to the second input of the first synchronizer and to the input of the second delay element, the first output of the pulse distributor is connected to the first inputs of the third and fourth synchronizers, and the second output to the first input of the fifth synchronizer, the clock input of the first delay element is connected to the input of the third element delay to the second input of the fourth synchronizer and is the input bus; the output of the second delay element is connected to the second input of the third synchronizer; the output of the third element the delays are connected to the clock input of the second delay element and to the second input of the fifth synchronizer, the output of the second synchronizer is connected to the summing input; the house of the second reversible counter,: the output of the third synchronizer is connected to the subtractive input of the second: reversible counter, the outputs through the second switch are OUTPUT bus Speed change period, the output of the fourth synchronizer is connected to the summing input of the third reversible counter, the output of the fifth synchronizer is connected to the subtractive input in the third reversible counter, the outputs of which through the third switch are the output bus Frequency, the third output of the pulse distributor is connected to the control inputs of the second and third switches, the reset inputs of the first, second and third reversal counters are combined and are bus reset. Speed