SU1179545A1 - Frequency-to-number converter - Google Patents

Abstract

FREQUENCY CONVERTER TO CODE, containing a clock pulse generator, pulse distributor, four cInxpo isolators, two OR elements, reversible counter, switch, two delay elements and two And elements, the output of the clock generator is connected to the pulse distributor, first, second, third and the fourth outputs of which are connected to the first inputs of the first, second, third and fourth synchronizers, respectively, the outputs of the first and second synchronizers through the first OR element are connected to the summing in the reversible counter, the outputs of the third and fourth synchronizers through the second element OR are connected to the subtracting input of the reversible counter, the outputs of which are connected to the output bus through the switch, the fifth output of the pulse distributor is connected to the control input of the switch, the installation input of the reverse counter is connected to the initial installation bus , the first input bus is connected to the first input of the first element And the output of which is connected to the second; the input of the first synchronizer and the first delay element — with the second input of the third synchronizer; the second input bus connected to the first input of the second AND element, the output of which is connected to the second input of the second delay element, characterized in that, in order to expand its functionality, He entered the register, trigger, third, fourth, fifth, and sixth ele ments (LIs and the third and fourth elements OR, the first control bus is connected to the first input of the register, the first output of which is connected to the second input The first element And, the second control bus is connected to the second input of the register, the second output of which is connected to the second input of the second element AND, the output of which is connected to the first inputs of the third and sixth elements and the second delay element is connected to the first inputs of the fourth and the fifth elements And, a third control bus connected to the installation input of the trigger, the direct output of which is connected to the second inputs of the third and fifth elements And, the fourth control bus connected to the reset input of the trigger, inverti the rutting output of which is connected to the second inputs of the fourth and sixth elements AND, you

Description

the moves of the third and fourth elements I. And the third element OR is connected to the second input of the second synchronizer, the outputs of the fifth and

of the sixth elements AND through the fourth element OR are connected to the second input of the fourth synchronizer.

The invention relates to a measurement technique and can be used to connect computers with control objects, to process signals from frequency sensors (including string accelerometers) in frequency stabilization systems.

The aim of the invention is to enhance the functionality of the converter by providing an additional mode for converting the sum of frequencies.

The drawing shows an inverter circuit diagram;

The converter contains 1 clock pulse generator, 2 pulse distributor, synchronizers 3-6, element OR 7, reversible counter 8, element OR 9, switch 10, output bus 11, initial setup bus 12, first input bus 13, element 14, element 15 delay, the second input bus 16, elements And 17-19, the element 20 delay, elements And 21

22, the first control bus 23, the register 24, the second and third control buses 25 and 26, the trigger 27, the fourth control bus 28, the elements OR 29 and 30.

The device works as follows.

If there are no signals on the control bus tires 23, 25, 26 and 28, the initial installation of the reversing counter 8 is made on the bus 12 and the duration of the installation signal must be not less than the delay time in the delay elements 15 and 20 for their complete cleaning. Then a combination of signals on tires

23.25, 26, and 28, the corresponding operating mode of the converter is set (see table).

When converting a frequency to a code on the first input, the input frequency is fed to bus 13, the signal from the first control bus 23 is fed to the first input of the register 24, the signal on the second control bus 25 corresponds to a logical O, and therefore the logical O will be on the second output of the register 24

Therefore, the element 14 is open, the element 17 is closed, and regardless of the state of the trigger 27, the input frequency pulses through the synchronizer 3 and the element OR 7 arrive at

j summing reverse input

the counter 8 and they are also through the delay element 15, the synchronizer 5 and the OR element 9, the code of the number equal to the integer part of the product will be set to the subtractive input of the reversing counter 8, the output of which is equal to the time of signal propagation in the delay element 15 time frequencies

J signal propagation in the delay element. The sign of the code is determined by the state of the two sign bits allocated for this purpose, i.e. the output code is a modified additional code.

The frequency conversion to the code on the second input differs from the conversion on the first input in that in this case the input frequency is fed to bus 16, the signal corresponding to logical 1 is fed to bus 25 and bus 26. In this case, the element 14 is closed and the element And 17 and, since the Q QOM output of the trigger 27 is a logical 1 state, elements 18 and 22 are open. The input frequency pulses from element 17 are transmitted through element 18 and element OR 29,

d synchronizer 4 and element OR 7

to the summing input of the reversible counter 8, and they are also through the delay element 20, the element AND 22, the element OR 30, the synchronizer 6, the element OR 9 - to the subtracting input of the reversible counter 8, which continuously tracks the frequency value on the second input.

The sum of the frequencies is converted into a code when the converted frequencies are simultaneously applied to both input buses 13 and 16. At the same time, a signal corresponding to logical 1 to bus 26 and buses 23 and 25 is supplied. Since in this case both elements AND 14 and 17 are open then the input frequency pulses from bus 1 pass through the AND 14 element, the synchronizer 3 and the OR 7 element to the summing input of the reversible counter 8 and through the delay element 15, the synchronizer 5 and the RSHI element 9 to the subtracting input of the reversing counter B, the input frequency pulses from ww 16 pass through u The elements AND 17 and 18, the elements OR 29 and 7 and the synchronizer 4 on the summing input of the reversible counter 8 and through the delay element 20, the element AND 22, the elements OR 30 and 9 and the synchronizer 6 - on the subtracting input of the reversible counter - 8. Thus, the summing input of the reversible counter 8 receives pulses of two input frequencies and through the delay elements 15 and 20 these frequencies arrive at the subtractive input of the reversible counter 8, and with the help of synchronizers 3-6 and distributor 2 the time separation of all the input pulses of reversing is carried out Meters withstand at 8. Therefore down counter 8 is carried out the addition of two frequencies, i.e., continuous monitoring of the sum of the two frequencies is carried out, with the sum sign always positive.

1795454

In the mode of frequency difference conversion, the logical 1 code is simultaneously applied to the control buses 23 and 25 and 28. The input frequencies 5 are fed to the buses 13 and 16. In this case, the elements AND 14, 17, 19 and 21 are open. In contrast to the sum conversion frequency in the code of the first input frequency from the bus 13 is fed to the summing input of the reversible counter 8 and through the delay element 15 to the subtracting input of the reversible counter 8, and the second input frequency from the bus 16 postt5 goes to the subtracting input of the reversible counter 8 and through the element; 20 delay - to the summing input rever 8. Thus, continuous monitoring of the frequency difference is carried out, the sign of the difference being positive if the first frequency is greater than the second, and negative if the first frequency is less than the second.

The output code of the reversible counter 8 is a modified additional one; therefore, in addition to the sign of the code, it is possible to detect overflow of the counter 8 by the state of the sign bits.

The signal from the fifth output of the distributor 2 is fed to the control input of the switch 10 and reads the code from the reversible counter 8 to the output bus 11 at times when there are no input pulses at the input of the counter 8.

0

 order to synchronizers

3-6 did not introduce significant time shifts and did not affect the accuracy of the conversion; the frequency of generator 1 should not be chosen; less than 5 times the maximum (according to the number of outputs of the distributor 2) the maximum value of the transamp frequencies.

Note.X is an arbitrary state.

Claims (1)

A FREQUENCY CONVERTER IN A CODE containing a clock generator, a pulse distributor, four clocks, two OR elements, a reversible counter, a switch, two delay elements and two AND elements, the output of the clock generator is connected to the input of the pulse distributor, the first, second, third and fourth the outputs of which are connected to the first inputs of the first, second, third and fourth synchronizers, respectively, the outputs of the first and second synchronizers through the first OR element are connected to the summing input Eversive counter, the outputs of the third and fourth synchronizers through the second OR element are connected to the subtracting input of the reverse counter, the outputs of which through the switch are connected to the output bus, the fifth output of the pulse distributor is connected to the control input of the switch, the installation input of the reverse counter is connected to the initial installation bus, the first input bus is connected to the first input of the first element And the output of which is connected to the second: the input of the first synchronizer and through the first delay element - from the second m input of the third synchronizer, the second input bus is connected to the first input of the second AND element, the output of which is connected to the second input of the second delay element, characterized in that, in order to expand the functionality, a register, trigger, third, fourth, the fifth and sixth elements AND and the third and fourth elements OR, the first control bus is connected to the first input of the register, the first output of which is connected to the second input of the first element And, the second control bus is connected to the second input of the register the output of which is connected to the second input of the second element And, the output of which is connected to the first inputs of the third and sixth elements And, the output of the second delay element is connected to the first inputs of the fourth and fifth elements And, the third control bus is connected to the installation input of the trigger, the direct output of which connected to the second inputs of the third and fifth elements And, the fourth control bus is connected to the reset input of the trigger, the inverting output of which is connected to the second inputs of the fourth and sixth elements And, the third outputs and a fourth AND gates via the third OR gate connected to the second input of the second synchronizer, the outputs of the fifth and | of the sixth element AND through the fourth element OR connected to the second input of the fourth synchronizer.