SU1325460A1 - Device for comparing numbers in residue system - Google Patents

Abstract

This invention relates to a computing tethnika. The purpose of the invention is to expand the range of the possible difference of compared numbers. The device contains p (by the number of bases of the system of residual classes) of switches and adders, 2π-2 encoders, (p-2) equality fixation blocks, OR elements and an analysis block containing triggers, AND, OR, NOT, OR-NOT, AND elements -NOT. The residues "i-a" and PI-pn of the compared numbers A and B are fed to the inputs of the device, then the differences | A-B | in the JUICE {pi, pg p „-.} and | B-AIX- The analysis block records cases, or cases when the device cannot compare A and B, because | A-B | p1p „. 1 hp ff, 2 ill. (L 00 N5 SL 4 O5

Description

The invention relates to computing.

The purpose of the invention is to expand the range of the application area by increasing the range of the difference of the compared numbers.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a block diagram analysis.

The device contains n switches 11 - n, where n is the number of bases of the residual class system (SOC), two groups of encoders 2i-2n-i and 3 | -3 „1, n adders 4i-4", (n-2) blocks 5i -5п-2 equality fixations, elements OR 6-8, analysis block 9, n groups of inputs of residuals of the first 10 and second 11 numbers, input 12, specify the order of comparisons of operands, input 13 of the initial setup, inputs 14 and 15 of synchronization, outputs "Equal 16, "Less than 17," More than 18, "Incomparable 19. The drawing also indicates the information inputs 20-22 of the analysis block 9.

The analysis block 9 contains elements AND 23-29, elements OR 30-32, elements NOT 33 and 34, elements AND-NO 35 and OR-NOT 36, triggers 37 and 38.

The device works as follows.

At the entrances 10 | -10p and lli -11 "receive the values of the residues of the numbers A and B oci-a" and p | -PP on the basis of the JUICE pi-p ". At the zero signal at the input 12 on the first and second outputs: the nd switch (r 1,2, ..., p), respectively, a, and p, and at the single — respectively, a, and p /, and at the single — respectively p / and a /. Adders 4i-4 „. | have one summing and two subtracting inputs, and with zero value at input 12 at outputs of this adder - value, - p, -f /, where f, - - value at output of the twoth encoder 2i-2 „1 first groups,. With a single value at the input 12 C, p, -a, -f, -.

The encoder 2 / (, 2, ..., p-1) converts the remainder, r -pnlj into the remainder Iv ilpt (or.-A; l (, / i into the remainder). The encoder 3 converts the value of Q into the value

(.} - Cj-Xjln, where 1 (modp, -).

Before the operation of the signal at input 13, the triggers 37 and 38 are set to the zero state. At the input 12 - the potential is zero, therefore on the VEI of encoders 3 | -3 „| values are formed

, - | | a „-р„ | р „| рс1е1 If, р,„ then ..., and if ..., then.

Magnitude

 , if

, if a ,

P

where r, -.

on the other hand

 pipn if and

С | В-Л | р р | р, ь if.

If C O, then L B.

If, after calculating А-B, „at zero signal at input 12 ... 0, then at the outputs of blocks 5i-5„ -2, equality is fixed, the element OR 6 and the input 20 of the analysis block 9 - the zero level, at the output of the element OR 8 - single level.

After the pulse at the input 14, the trigger 37 is set to one, which leads to the appearance of a logical unit at the output of “More than 18 devices. ,

If, after calculating АB | p „/ ..., then at the output of the elements OR 6 and 8 - zero levels, which leads to the appearance of a logical unit at the 0 output“ Equal to 16 devices.

If the output of a block 5i - 5l - 2 signal of a logical unit, then either, or. In the latter case, the device cannot determine the ratio of the numbers A and B. Input 12 is given a signal of a logical unit, and then after the termination of transient processors, a pulse is output 15.

Similarly, after calculating | B-L | p, if ..., then the output of the blocks 5 | -5n-2, the element OR 6 and the input 20 of the analysis block 9 is zero, the output of the element OR 8 is one, that after the pulse input 15 causes the flip-flop 38 to be set to one.

After the computation of AND-B ,, and 5 IB- / 1 | p, the triggers 37 and 38 indicate the result of the comparison:

five

0

Triggers 37 38

About About 1 1

O 1 o

A is incomparable with B, since 1 A-B I pip ,,

Claims (2)

Invention Formula I A device for comparing numbers in the system of residual classes, containing n adders, where n is the number of bases of the system, three OR elements, a unit for fixing the equality of numbers, the output of which is connected to the first input of the first OR element, differing from the fact that by increasing the range of the difference of the compared numbers, n switches were introduced into it, two groups from (p-1) encryptors each, (p-3) units for fixing equality of numbers and an analysis unit, with the group of inputs of bits i-ro of the remainder of the first and second numbers, where i 1,2, ... ", are connected respectively to the first and second groups of information inputs of the t-ro switch, the first and second groups of outputs of which are connected respectively to the Summing MUM and the first subtractive inputs of the I-th adder, the outputs of the n-th adder are connected to the inputs of the second OR element and the output of the / th encoder of the first group, where / 1,2, (n-1), is connected to the second you reading input of the / -th adder, the outputs of which are connected to the inputs of the / -th encoder of the second group, the output group of the k-ro encoder of the second group, where k 1, 2, ..., (p.-2), is connected to the first group of inputs th block of equality fixation, group of outputs () -ro of the encoder of the second group is connected to the second group of inputs of fe-ro block of equality fixation, output of 1st block of equality fixation, where / 2,3, ..., (p-2) connected to the / -M input of the first element OR, the group of outputs of the (n-1) -th encoder of the second group is connected to the inputs of the third element OR, the outputs of the first, second and third e The OR elements are connected to the first, second, and third information inputs of the analysis unit respectively, the input order for comparing the device operands is connected to the control inputs of all switches, the initial setup input of the device is connected to the initial setup input of the analysis unit, the first and second synchronization inputs of the device are connected with the first and second synchronization inputs of the analysis block, the outputs are Equal To, Less, No More, Which are incomparable, respectively The Equals, Less, More and "incomparably device. 0 2. The device according to p., Characterized in that the analysis block contains seven elements AND, three elements OR, two elements NOT, element NAND, element OR-NOT and two triggers, and the first information input of the analysis unit connected to the first inputs the element OR NOT, the first and second elements AND, and through the first element NOT with the first inputs of the third and fourth elements AND, the outputs of the latter are connected to the first inputs of the first and second elements OR, respectively, whose inputs are connected to the installation inputs of the first state respectively o and second flip-flops, the direct outputs of which are connected to the first inputs of the fifth and sixth elements AND, respectively, as well as the first and second inputs of the AND-NOT element, the output of which is connected to the second inputs of the fifth and sixth elements And, the first input the seventh element AND and the input of the second element NOT, the outputs of which are respectively the outputs "More," Less, "Equal, and" Incomparably the analysis unit, the input of the initial installation of the analysis unit is connected to 5 inputs for setting the first and second triggers to the zero state; the first synchronization input of the analysis unit is connected to the second inputs of the first and third elements, And the second synchronization input of the analysis unit is connected to the second inputs of the second 0 and the fourth And elements, the second and third information inputs of the analysis unit are connected respectively to the first and second inputs of the third OR element, the output of which is connected to the third inputs of the third and fourth And elements and to the second 5 input element OR NOT, the output of which is connected to the second input of the seventh element AND, the outputs of the first and second elements AND connected to the second inputs, respectively, of the second and first elements OR. 10, p, / go i "I -f 1 fu2. FIG. g 1 W jvi