SU1644147A1 - Majority-redundant device - Google Patents

Abstract

The invention relates to computing and can be used to build highly reliable redundant systems. The purpose of the invention is to increase productivity and expand the field of application of the device. The device contains a NOT element, three AND elements, reserved blocks, a majority block and a decoder. The essence of the invention is to determine the presence of a single code at the outputs of most of the reserved blocks with the subsequent zeroing of these blocks. 1 hp f-ly, 2 ill.

Description

The invention relates to computing and can be used to build highly reliable redundant systems.

The purpose of the invention is to increase productivity and expand the field of application of the device.

The invention consists in determining the presence of a single (code at the outputs of most of the reserved blocks and zeroing all the reserved blocks when the next signal arrives on the sync bus.

FIG. 1 shows a diagram of the device; in fig. 2 is a decoder circuit.

The device contains the element NOT 1, the third 2 and the first 3 elements And, the reserved blocks 4, the majority block 5, the decoder 6, the second element And 7, information input 8, the output bus 9.

The decoder (logical block) 6 contains the elements AND 10 and 11 by the number of reserved blocks, the element OR 12.

The device works as follows.

Bus 8 to the input elements And 2 and 3 receives the synchronization signals. In the absence of a block 5 code that contains units for all bits, the output of the element And 7 produces a zero signal, which is fed to the inputs of the elements And 11. At the outputs of the elements And 11, zero signals are applied to the inputs of the element OR 12. As a result at the output of the element OR 12, a zero signal is formed, blocking the appearance of the signals at the output of the element And 3 and entering the input (element NOT 1. From the output of the element NOT 1, the input signal And 2 receives a single signal, allowing the transmission

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signals from bus 8 to the installation inputs of blocks 4. With the arrival of the signal, blocks 4 modify their state and generate output signals at the bit outputs. Block 5, one by one, majorizes signals coming from the outputs of block 4. From the outputs of block 5, signals arrive at the output bus 9 of the device and at the inputs of the And 7 element.

If there are single signals in all bits of the code at the output of block 5 at the output of element And 7, a single signal is generated that arrives at the decoder 6 at the inputs of elements 11. At the same time, the signal codes from the outputs of block 4 arrive at the inputs of elements 10. give out single codes (units at the output of block 5), then from the outputs of elements And 10, to which these single codes fall, single signals will be recorded. As a result, single signals arrive at both inputs of the AND 11 elements and single signals are also generated at the outputs of the inputs to the inputs of the OR 12 element. At the output of the OR 12 element, a single signal is formed that connects bus 8 through the AND 3 element to the zeroing inputs of the 4 blocks. a single signal from the output of the element OR 12 is fed to the input of the element NOT 1, from the output of which a zero signal is removed, the locking element AND 2 and disconnecting the bus 8 from the information inputs of the blocks 4.

If a major block 5 or output bus 9 fails, such that a single code is formed on the output bus 9, and not a single code is removed from the outputs of blocks 4, then a single signal is output from the output of the And 7 element, and a zero signal from the And 10 of the output of the And 10 elements the outputs of blocks 4 are not in the unit state), the outputs of the elements 11 and the zero signal and the output of the element OR 12 will not form a single signal that would open the circuit 3 for passing the zeroing pulse.

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The device has an increased speed and does not require an additional synchronization bus, which allows it to be used in a whole range of new applications.

Claims (2)

1. The primary backup device containing the major block, the first and second And elements, the reserved blocks and the decoder, the first input of the first And element is connected to the information input of the device, and the output is connected to the zero inputs of the reserved blocks, the output group of which is connected to the corresponding group of inputs majority unit and to the corresponding group of information inputs of the decoder, the group of outputs of the majority block is connected to the output bus of the device and to the group of inputs of the second element I, the output of which is connected to the synchronous input of the decoder, the output connected to the second input of the first element I, characterized in that and expanding the field of application of the device, the third AND element and the NOT element are entered into it, the information input of the device is connected to the first input of the third AND element, the output of which is connected to info mation blo.kov redundant inputs and the second input - to the output of the decoder via the NOT element. 2. The device according to claim. 2, the decoder contains the first group of AND elements by the number of groups of information inputs, the second group of AND elements and the OR element, and the inputs of each of the AND elements of the first group are associated with the corresponding group of information inputs of the decoder; Both the first group are connected to the first inputs of the AND elements of the second group, the second inputs are connected to the synchronizer input of the decoder, and the outputs to the inputs of the OR element, the output of which is the output of the decoder. 1 2