SU1662006A1 - Device for t-code compression - Google Patents

Abstract

The invention relates to computing and data transmission, can be used to compact T-codes. The purpose of the invention is to expand the functionality of the device by compacting codes with a variable value T. The device contains a reversing shift register 1, the element OR - AND 4, the counter 3, the element AND 5 and the element OR 6 with corresponding links. The device can be used in arithmetic logic, storage devices and data transmission systems. 1 il.

Description

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The invention relates to computing and data transmission, can be used to compact t-codes,

The aim of the invention is to extend the functionality by compacting codes with a variable value of t.

The drawing shows a diagram of a device for compacting t-codes.

The device contains a reverse shift register 1, an input 2 of the device constants, a counter 3, an OR-AND 4 element, an AND 5 element, an OR 6 element, a device information input 7, a device clock input 8, a device output 9, and a device mode setting input 10.

Minimal and optimal t-codes, minimal and optimal t-number system, packet format code, packet-optimal t-code form can be represented in a generalized form

Ft (n) 00 1J OCL: 0 ..,. .O; (1) hio - igi tk

t cumin,

where cmin and r are constant numbers for each specific form and given t; k is the number of packages of units. For transmission or storage, it becomes necessary to compact this code in order to use the communication channel or memory elements more efficiently, which are to a small extent subject to interference if the t-code is condensed due to the elimination in the package of d-1 units and cmin zeros after each first units of the package, it is possible to restore the t-code by the subsequent introduction of missing characters.

The operation of the device is based on the non-synchronization of g-1 units and cmin zeros. The versatility of the device lies in its ability to use it for t-codes of the form (1), by changing the value of the input 2 of the constant, to which the inverse (reverse code) value of the number of mines is supplied.

Shift register 1 is designed to write a compressed code combination by the high bits ahead and then read it by the low bits ahead on output 9.

Counter 3 is designed to count the number of cpmin zeros, after which it opens the register 1 synchronization through the OR-AND 4 and AND 5 elements; when the single signal arrives at input 7, the contents of the counter 3 are zeroed.

The device works as follows.

Let it be in the initial state, in which the reverse (inverse) code cmin is inputted to input 2, and the counter 3 is blocked by a single potential at the output of the OR-4 element by means of sync pulses at input 8: Input (7) older bits ahead, synchronize respectively with input 8. Since counter 3

0 is blocked, before the first unit of the first packet all zeros are synchronized in the shift register 1 and written to it. With the arrival of the first and subsequent units of the packet at input 7, the counter 3 is reset to the zero state, while the first unit is written to the shift register 1, and there are no subsequent ones, since the output potential of the element OR-AND 4 after the first unit is zero.

0 which closes the element AND 5. The following after the package of units, the cmin of zeros are also not synchronized, until the output of the element OR-AND 4 is set to one. The sum of the potentials of the inverse code at input 2 and the direct code of the cummin at counter 3 triggers the element OR-4. Thus, the state of input 2 determines the conversion factor. In the next, all the remaining zeros of the code after tmin are written to shift register 1. Due to the periodicity of the interleaving of a packet of g units and the cumin of zeros, the described cycle is repeated.

5 The device compresses the minimum and optimal t-codes, the optimal t-numbering system is a maximum of t + 1 times, the packet form of the t-code for t 1 to a maximum of 5 times, for t 1 to a maximum of t + 2

0 times, batch-optimal for t 1 maximum 3 times.

Claims (1)

The invention The device for compacting t-codes, containing a reverse shift register, a counter and an element, the information input of the device connected to the installation input in the counter O and the information input of the reverse shift register, the output and input of setting the shift direction of which are connected respectively to the output and input of the device mode setting, the clock input of which is connected to the clock input of the counter and the first input 5 of the And element, the output of which is connected to the clock input of the reverse shift register, characterized in that, in order to extend the functionality by compacting codes with a variable value of t, it contains the element at OR-I and the element OR, and the outputs are separated, respectively, with inverse counters of the counter connected to the first input of the counter and information of the corresponding groups by the device input, the inputs of the OR-AND input bits, the output of which is connected to the second constant of connected to the second input element AND and the first input element-5 inputs of the corresponding groups of the element OR, the output and the second input of which is so-OR-AND.