SU1767701A1 - Decoder - Google Patents

Abstract

The invention relates to computing and data transmission, can be used for the sequential encoding of a 2-character code. The purpose of the invention is to expand the scope of use due to the possibility to encode a 2-character code. The goal is achieved by introducing into the device containing the shift register 1, the element AND 3, the elements OR 4 and 5, the trigger 7, the prohibition element 6 with the corresponding connections. The device can be used in arithmetic logic devices, for constructing highly reliable memory devices, in systems with high requirements for the reliability of information, with a high level of interference, with the sequential transmission and processing of a 2-character code. 1 il.

Description

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The invention relates to computing and data transmission, can be used for the sequential encoding of a 2-character code.

The aim of the invention is to expand the scope of use by being able to encode a 2-character code.

The drawing shows a diagram of a device for coding,

The device contains the shift register 1, input 2 of the initial setup of the device, element AND 3, the second element OR 4, the first element OR 5, prohibition element 6, trigger 7, information input 8 of the device, output 9 of the device, clock input 10 of the devices.

In the 2-character code, the unit is represented as 10, and zero-01, it is possible to determine the type of error 0-1 or 1-0 with distortion, i.e. 00 in the code pair indicates a 1–0 transition, and a 11 –0 0–1 transition, where the allowed code pairs are 10 and 01. A 2-character code allows all single and double errors to be determined, except for symmetrical ones in the code pairs.

The device works as follows.

Register 1 enters the information in the binary system, then trigger 7 is set to state 1 by a pulse at input 2. The device is now prepared for encoding into a 2-character code, the code combination of which goes to output 9. When trigger 7 is set to - nii 1, information from register 1 enters the circuit; elements AND 3 and OR 5 to output 9 in direct form, in case the trigger is in the state O, then in the inverted form through elements 4 and 5. Thus, the first character of the code pair of the 2-character code is written in in the inverted form, the 0 symbol (the sync pulse) is less than T (trigger trigger 7), otherwise it is necessary to put a delay element after trigger 7). The trigger 7 and the prohibition element b provide for the division of the frequency of the synchronization pulses applied to register 1 by two times, since two symbols in a 2-character code correspond to each character in the binary system. If necessary, the resulting 2-character code can be accumulated by means of a shift register synchronized by pulses from the input 10 of the device.

Claims (1)

Claim device A coding device comprising a shift register, an AND element, first and second OR elements and a trigger, the device clock input being connected to a trigger trigger input, the output of which is connected to the first input of the AND element, the output of which is connected to the first input of the first OR element, characterized in that, in order to expand the scope of use by coding a two-character code, it contains a prohibition element, and the information input of the device is connected to the information input of the shift register, the output of the cat The first is connected to the second input of the AND element and to the first input of the second OR element, the inverse output of which is connected to the second input of the first OR element, the output of which is the output of the device, the initial installation input of which is connected to the second input of the first 1 trigger, whose output is connected with the second input of the second OR element and with the control input of the prohibition element, the output and information input of which are connected respectively to the clock input of the shift register and the clock input of the device.