SU1707761A1 - 2-k-bit gray code counter - Google Patents

Abstract

The invention relates to digital computing and can be used for sampling in the Gre code. The purpose of the invention is to simplify and increase the speed of the counter by an even number of bits. The counter contains (ZK - 1) triggers 3-1 - З + зк-1. the synchronous input of each (2P-1) -th trigger is connected to the synchronous input of the 2P-th trigger, the synchronous input of the (2K-1) -th trigger is connected to the synchronous input of the 2K-th trigger, the first output of each (2P-1) -th trigger is connected to (2P -1) -th counter output and with the first information input of the 2P-th trigger, the first output of the (2K-1) -th trigger is connected to the (2K-1) -th output of the counter and the information input of the 2K-th trigger, the second output of which is connected with the information input of the (2K-1) th trigger, the second output of each 2P-th trigger is connected to the information input of the (2P-1) th trigger. 2 Il. THX

Description

The invention relates to digital computing, mainly on integrated logic elements made, for example, by CMOS technology.

Digital devices are widely used in the Gre code (reflex, adjacent) that can be used in converters, since when exposed to a counting pulse with an insufficient duration, the error does not exceed the counting increment 1. In addition, the adjacent coding provides a reduction in the dynamic component consumed power.

Known n-rezdny counter in the Gre code, containing (n + 1) TV (CC) triggers. This device has the following disadvantages: heterogeneity of structure. The number V (l, K) of the inputs grows linearly to the value of n; high hardware costs. So, when using CMOS technology for building one IK trigger, 30 transistors are required, a logic element with a total number of

l (n + 1)

inputs, - - y - 1

than n (n + 1) - 4 CMOS transistors. The total number of transistors is n + 31n - 4; poor performance in the dividing mode, due to additional delays in the input logic of IK triggers, which depend on the bit size.

The closest to the proposed is an n-bit counter in the code Gre, co. which requires no less

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holding (2n-1) T-flip-flops, each of which can use a D-flip-flop, the second output of which is connected to its information input. This device has uniformity and regularity, is well implemented on similar CMOS ICs (for example, K561TM2 ). It has a high speed in the separating mode, however, it has the following disadvantages: large hardware costs (number of D-flip-flops (2n-1); low speed in the control mode, characterized by a delay of nD-flip-flops.

The purpose of the invention is to simplify and increase speed in the control mode.

The goal is achieved by the fact that in a 2K bit counter in the Gre code, which contains input, 2K outputs, where K 1,2 ..., (ZK-1) triggers, and the input of the counter is connected to the synchro of the first a trigger, the first output of every 2P, where P 1, 2, ..., (K-1) of the trigger is connected to the synchronous input of the (2K- | -1) -th trigger, the second output of each 2P-second trigger is connected to the synchronous input ( 2P + 1) -th trigger, the first and second outputs of each (2K + + P) -th trigger are connected in pairs, respectively, with the 2P-th output of the counter and information input (2P + P) -th of the trigger, and the first output 2K- first trigger connected to 2 - output of the counter, the synchronous input of each (2P-1) -th trigger is connected to the synchronous input of the 2P-th trigger, the synchronous input of the (2K-1) -th trigger is connected to the synchronous input of the 2K-th trigger, first output of each (2P-1) -th trigger connected to the (2P-1) th output of the counter and to the first information input of the 2P-th trigger, the first output (2K-1) of the first trigger is connected to the (2K-1) th output of the counter and information input of the 2K-th trigger, the second output of which is connected to the information input (2K-1) of the trigger, the second output of each 2P-th trigger is connected to the information input (2P-1) of the first trigger .,

Figure 1 shows the proposed counter; figure 2 - timing diagram of the counter.

The counter contains the input 1, 2K outputs (K 1. 2, ..). 2-1. 2-2. 2-3. 2-4 .... 2- (2K-2).

2- {2K-1), 2-2K. (ZK-1) trigger Z-1 ...., 3- (ZK-1): the input 1 of the counter is connected to the synchronous input of the first trigger 3-1, the first output of each 2P, where P 1, 2 ..., (K-1) trigger

3-P is connected to the synchronous input (2K + P) of the trigger. 3- (2УР) the second output of each 2р-nd trigger 3-2Р is connected by a synchronous input (2Р + 1) -th trigger 3- (2Р + 1) the first and second outputs of each () -th trigger ЗЧ2К + Р) are connected in pairs respectively 2P-m

the output of the counter 2-2P and information input (2K + P) th trigger ZCh2K + P).

The first output of the 2K-th trigger 3-2K is connected to the 2K-m output of the counter 2-2K. The synchronous input of each (2P-1) -th trigger 3- (2P-1) is connected with the synchronous input of 2P-th trigger 3-2P. The sync-input (2K-1) -th trigger 3- (2K-1) is connected to the synchronous input 2K-th trigger 3-2K, the first output of each (2P-1) -th trigger 3- (2P-1) is connected to (2P- 1) th output of the counter 2- {2P-1) and with the information input of the 2P-th trigger 3-2P, the first output of the (2K-1) -th trigger 3- (2K-1) is connected to (2K-1 m output counter 2- (2K-1) and the first information input of the 2K-th trigger 3-2K, the second output of which is connected to the information input of the (2K-1) -th trigger 3- (2K-1) second output of each 2P-th trigger 3 -2P is connected to the information input (2P-1) of the 3rd trigger (2P-1).

The operation of the counter is illustrated in a time diagram (FIG. 2). Let, in the initial state, all the triggers 3-1 ..., 3- (3K-1) are set to the logical zero state. The installation R-inputs in figure 1 is not shown, but can be, if necessary, entered into the counter. Each trigger 3-1 ..... 3- (ZK-1) switches along the pulse edge at its sync input. The diagram shows the signal at input 1, consisting of pulses: 1, 2, 3, 4, ..., 8, 9 ..... 2P D .... 3-2P 3 ..... 2P 1 ..... 2P. (n - 2K). The oscillograms of the outputs of the counter and the first outputs of all the triggers are shown (figure 1).

Thus, the proposed 2K-resdny counter contains (ZK-1) D-triggers, which is K (25%) less than in the known. In the control mode of operation, the minimum period of impulses following input 1 is determined by the delay of the () th trigger, which is two times less than the known one. The proposed counter has a higher speed in the dividing mode, is characterized by the regularity of the structure, which, when built on the library elements of CMOS-LIS, provides less hardware costs.

Claims (2)

Claims of the invention 2K-bit counter in the Gre code, containing the input. 2K outputs, where K 1, 2 ..., (ZK-1) of the triggers, the input of the counter is connected to the synchronous input of the first trigger, the first output of every 2P-th, where P 1. 2 .... (K-1) -th trigger is connected to the sync input (2K + P) -th trigger, the second output of each 2P-th trigger is connected to the sync input (2P-I) -th trigger, the first and second outputs of each (2K + P) th trigger are connected in pairs, respectively, with the 2P-th output of the counter and information input (2K-F} -th of the trigger, and the first output of the 2K-th trigger is connected with the 2K-th output of the counter, which , in order to simplify and improve speed, the synchronous input of each (2P-1) -th trigger is connected to the synchronous input of the 2P-th trigger, the synchronous input of (2K-1) -th trigger is connected to the synchronous input 2K-th trigger, the first output of each (2P The 1} th trigger is connected to the (2P-1} th output of the counter and to the information input of the 2Р-th trigger, the first output of the (2K-1) th trigger is connected to the (2K-1) th output of the counter and the 2K information input th trigger, the second output of which is connected to the information input of the (2K-1) th trigger, the second output of each 2P-th trigger is connected to the information input of the (2P-1) -th trigger. 2; 2J ")