RU1775854C - Controlled pulse recurrence frequency divider - Google Patents

Abstract

Application: the invention relates to digital technology and can be used in devices of measuring technology, automation and telemechanics. Summary of the invention: the device comprises a pulse counter (1), a comparison circuit (2), a register (3), a D-flip-flop (4), a code bus (5), an input bus (6), an output bus (7) with corresponding communications mi 2 ill.

Description

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The invention relates to digital technology and can be used in measuring devices of automation and telemechanics

A controllable pulse repetition rate divider comprising a binary pulse counter is known, the counting input of which is connected to the input bus, and the bit outputs are connected to the first inputs of the corresponding coincidence elements, the second inputs of which are connected to the control code buses, and the outputs to the inputs of the OR element, the AND-NOT element, the output of which is connected to the installation input of the binary pulse counter and the first input of the NOT-OR element, the second input of which is connected to the output of the OR element, and the output - with the first input of the element 1L-NOT, the second input d soedinech which the input bus.

An advantage of the known divider is that the change of the divisor of the divider occurs simultaneously with the change of the controlled code on the buses

A disadvantage of the known divider is its low stability due to the lack of synchronization of the change in the control code of the division coefficient at the inputs of the matching elements with the pulses of the input sequence.

The closest in technical essence is a controllable pulse repetition frequency divider containing a summing pulse counter, the clock input of which is connected to the input bus, the bit outputs of the counter are connected to the first inputs of the comparison circuit, the second inputs of which are connected to the outputs of the register, the information inputs of which connected to the control buses by the code of the division coefficient, the output of the comparison circuit is connected to the S-input of the first trigger, the direct output of which is connected to the first input of the first element AND-NOT and D-in the second trigger, the direct output of which is connected to the first input of the second NAND element, the output of which is connected to the output bus and the counter input, the C-input of the second trigger is connected to the output of the first NAND gate, the second input of which is connected to the second input of the second of the AND-NOT element and the input bus, the counter status O output is connected to the R-inputs of the triggers and through an inverter with a clock input of the register.

The comparison circuit in the known device is made on matching elements, the first inputs of which are connected to the bit outputs of the counter, the second to the outputs of the register, the outputs of the matching elements are connected to the inputs of the element

OR, the output of which is the output of the comparison circuit, i.e., the comparison circuit is designed as a matching circuit of the counter codes and the register.

The advantage of this divider is its high stability when changing the code of the division coefficient on the code bus due to the synchronization of changing the contents of the register with the output signal

0 counter when setting all its bits to zero.

The disadvantage of the divider is the long reaction time to a change in the control code, i.e. the inertia of the divider is large,

5 due to the impossibility of changing the divisor ratio of the divider to the end of the current cycle, because the information in the register is changed by the signal from the counter output when it is set to zero, which in turn leads to a decrease in the accuracy of the division of the input frequency when the division coefficient of the device changes.

The purpose of the invention is to increase the accuracy of dividing while simplifying the device. This is achieved by reducing the response time to a change of control code.

FIG. 1 is a structural diagram of a divider; FIG. 2 - time charts explaining his work. The divider contains a subtracting counter 1, the code outputs of which are connected to the first group of inputs (A) of the comparison circuit 2, register 3, the outputs of which are connected

5 with the second group of inputs (B) of the comparison circuit 2, the output (more) of which is connected to the D-input of trigger 4, the output of which is connected to the R-input of counter 1, the transfer output (state zero) of counter 1 is connected to the S-input trigger 4, code bus 5 is connected to the information inputs of register 3, the clock inputs of the counter 1, register 3 and trigger 4 are connected to the input bus 6, the output bus 7 is connected to

5 output counter transfer 1.

The device operates as follows. The initial state of the divider is provided by presetting trigger 4 when power is turned on at the R input (in Fig. 1,

0 shown). The work of the divider begins on the first working edge of the pulse received from the input bus 6. The current code from the subtracting counter 1 (Fig. 26) is compared by the comparison circuit 2 with the code in the register

5 3 (Fig. 2a), while the output of the comparison circuit 2 remains high until inequality A B (Fig. 2d) is satisfied. After the arrival of the working front O - 1 pulse from the input bus 6, if the inequality A B is violated, then the output

comparison circuit 2 is set low (Fig. 2d). which arrives at the D-input of trigger 4. Front 1 - 0 of the input signal from bus 6 (Fig. 2c) sets the output of trigger 4 to a high level (Fig. 2e), which resets counter 1 to the zero state. The signal from the output CR of counter 1 goes to the output of the divider and the S-input of trigger 4, sets the output level to low and allows the counter 1 to work on the clock input (Fig. 2e). On the first working edge, counter 1 is set to the state corresponding to its maximum code (Fig. 2 shows a diagram for the case of maximum counter code 1 equal to 15), and then the counter code is reduced to equal it with the control code, i.e. before inequality A B is violated, the next divider operation cycle ends. When the control code on the control buses 5 is changed before the end of the operation cycle, the divider with the first edge 0 - 1 of the input signal on bus 6, the new code is written to register 3 (Fig. 2a) and goes to the comparison circuit 2. If inequality AB is immediately violated, then the cycle ends. If the violation of inequality A B does not occur immediately, then the operation of the divider continues until the violation of this inequality.

The duration of the period of the output pulses of the divider, taken from the output zero (CH) of the counter 1, is determined by the formula:

T to (N + 1 - K), where to is the period of the input frequency,

N is the capacity of the subtracting counter,

K is the code on the control buses (defined in binary code).

The duration of the output pulses is |.

Thus in FIG. 2 shows the divider operation diagrams for three possible cases:

1) the control code recorded in register 3 is 9 (B 9), the divider cycle ends when counter 1 reaches state 9 (A 9),

2) the control code in register 3 during the operation cycle changed and became equal to 13 (B 13), while the state of counter 1 became equal to 11 (A 11), the inequality A B (11 9)

violated because A - And a B was equal to 9. l became equal to 13, therefore, the cycle of work of dividing bodies ends immediately;

3) the control code in register 3 during the cycle of operation changed and became equal to 8 (B 8), while the state of counter 1 became equal to 14 (A 14), the inequality A B was not violated, the cycle continues until the inequality is violated And B (14 8), i.e. The divider operation cycle will end when the counter code 1 matches the new control code equal to 8.

The considered divider can be implemented on the elements of the K561 series subtracting counter 1 -K561IE14,

comparison circuit 2 - K561IP2,

register 3 -K561TMZ,

trigger 4 -K561TM2.

Thus, the controllable pulse repetition rate divider under consideration makes it possible to increase the accuracy of division by reducing its inertia, due to the fact that the divisor factor of the divider can be changed before the end of the current cycle and due to a decrease in the influence of the uncertain state of the pulse counter in code change moment.

Claims (1)

The claims A controlled pulse repetition rate divider containing a pulse counter, the clock input of which is connected to the input bus, the bit outputs are connected to the first group of inputs of the comparison circuit, and the transfer output of the pulse counter is connected to the setup input of the D-trigger, a register whose information inputs are connected to code bus, and the information outputs of the register with the second group of inputs comparison circuit, characterized in that, in order to improve the accuracy of division while simplifying the controlled frequency amplifier, the comparison circuit is made in the form of an inequality circuit, and the pulse counter is subtracted, and the clock input of the shift register is connected to the input bus, the output of the More comparison circuit is connected to the D-input of the D-trigger, the output of which is connected to the input setting the pulse counter, the clock input of the D-trigger is connected to the input bus, and the output bus of the device is connected to the transfer output of the pulse counter. B CSI : Ј i 3 L