SU1522202A1 - Device for multiplying frequency by code - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in the synchronization systems of devices of a computer complex operating at different operating speeds. The aim of the invention is to expand the field of application and improve the workability. The device for multiplying the frequency by the code contains a discriminator 1, two diodes 2.3, an integrator 4 and a controlled oscillator 5 of the output frequency interconnected functionally, and the discriminator 1 contains a reversible counter 6, a comparison circuit 7, two triggers 8.9, a generator 10 clock pulses, seven elements AND 11-17 and the element OR 18 interconnected functionally. The principle of operation of the device consists in the separation by means of a discriminator of 1 periods of input frequency signals into successive measuring and adjustment periods. In the measurement period, the sign of the mismatch and the code of the number of periods of the output frequency are determined, and in the adjustment period the corresponding adjustment of the output signal is made. 1 il.

Description

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The invention relates to automation and computing and can be used in the synchronization systems of the computing complex devices operating at different operating speeds.

The purpose of the invention is to expand the scope and application of sustainability of work.

The drawing shows a functional -scheme of the device for multiplying the code parts.

The device contains a discriminator 1, the first and second diodes 2a 3, the integrator 4 and the control oscillator 5 of the output frequency, connected interconnectedly, functionally,.

The discriminator i contains a n-bit d-counter 6, comparison circuit 7, first and second triggers 8, 9, reHe-- pa torus 10 clocks, first, second, third, fourth, fifth, sixth and the seventh elements AND P-17 element OR 18 interconnected functionally.

The principle of operation of the device is to separate the input frequency signals by the discriminator PERIODS into successive Measurement and Adjustment periods. The last separation is carried out by the signals from the output of the trigger 8, to the counting LEC of which the input frequency signals are received,

In the measurement period, a determination is made of the error sign and the code of the number of output frequency periods generated during the period of the input frequency. This code is fixed on the counter b at the end of the measurement period j and the mismatch sign is on trigger 9 and the mismatch sign has a negative value (one trigger state 9), if the code on counter 6 is greater than the code on the frequency multiplication buses,

The change of the output frequency in the adjustment period is carried out by developing at the outputs of the elements I i i 1 or 11 and depending on the state of trigger 9, the time signal, which changes the potential at the output of the integrator 4, respectively.

The adjustment time of the ESh output frequency is numerically equal to the product of the period of the signals at the output of the generator 10 by the difference between the code set on the counter 6 in the beginning of the period

five

adjustment, and the code on the frequency multiply tires,

The frequency gain in the device should be determined by the ratio

ten

15

20

25

thirty

35

40

45.

50

55

TO

ten

one,

5 My CS

where the frequency of the signals at the output of the generator 10;

 max is the maximum frequency of the signals at the output of the controlled oscillator. ra 5,

This ratio is necessary for the frequency adjustment process to end during the pediod adjustment.

The measurement mode starts from quenching counter b and flip-flop 9, with the falling edge of the input frequency signal fp) being set to a Coupling, trigger state 8. Determining the code for the number of periods of the output frequency during the period of the input frequency is performed by driving the counting input counter b signals from the output of the generator 5,

The counter 6 in the measurement mode operates in direct counting mode, and in the event of a signal appearing at the output of the comparison circuit 7, the trigger 9 is set to unit state. Setting trigger 9 to state state characterizes that a negative frequency error is fixed in the device.

The input frequency signal .f device enters the adjustment mode ,,

In the adjustment mode, depending on the value of the signals at the output of the comparison circuit 7 and the output of the flip-flop 9, there are three cases;

The absence of adjustment, oscillator frequency 5, the D-nny case is characterized by the ratio f ",. -mf i.

. Odi. BX

where m is the code value on the frequency multiplying buses.

Adjusting the frequency of the generator 5 with a negative mismatch, this case is characterized by the ratio fjj, mf g ,,

Adjusting the frequency of the generator 5 with a positive mismatch. This case is characterized by the ratio Hz,: tG ,,

In the first case, the adjustment of the output frequency of the generator 5 is not performed and the operation of the counter 6 of the discriminator 1 at the counting input is prohibited.

In the second case, the adjustment is made to reduce the frequency of the output signals of the generator 5 and the discriminator counter 6 operates in the countdown mode.

In the third case, the adjustment is made by increasing the frequency of the output signals of the generator 5 and the counter 6 of the discriminator I operates in the direct counting mode.

Adjusting the frequency of the output signal according to the inputs of the first group of the comparison circuit, the output of which is connected to the first input of the fourth element Ai with the synchronous input of the second trigger, the direct output of which is connected to the first, inputs of the first, second and seventh elements And, the output of the generating pulses is connected to the first vko- 0 house of that element And, my way out

the first trigger is connected to the input I111I

installation in 1 of the second trigger, the first inputs of the third and sixth elements And the second inputs of the device fourth quarter stops at the fifth and seventh elements And, the output of the single signal on the output of the first And is connected with the second inputs of the first, the second and fifth elements And, the outputs of the third and fifth elements And connected with the first and

20 second inputs of the element OR, the output of the sixth element And is connected to the inputs of the installation in O of the second trigger and reversible counter, the reverse input of which is connected to the output

25 of the seventh And element, the frequency input of the device is connected to the second input of the sixth And element and the synchronous input of the first trigger of the discriminator, the bit inputs of the device multiplication code bus are connected respectively to the inputs of the second group of the discriminator comparison circuit, the output of the controlled output frequency generator of the device is connected to the output device and with, the second input of the third element And the discriminator, the output of the first element And which is connected to the positive electrode of the first diode of the device, and the output of the second element And comparing the discriminator 7 diskrimiskhemy i, after which the next input signal frequency t in a measuring device is transferred mode.

Claims (1)

Invention Formula A device for multiplying a frequency with a code containing serially connected input frequency bus, a discriminator, first and second diodes, an integrator and a controlled output frequency generator, characterized in that, in order to expand the scope and increase stability of operation, the input p-bit is the bus of the multiplication code, and the discriminator contains a reversible counter counter, a comparison circuit, the first and second triggers, the clock generator, from the first to the seventh AND elements, and the OR element, whose output connected with account35 responsibly with the inputs of the first group of the comparison circuit, the output of which is connected to the first input of the fourth element Ai with the synchronous input of the second trigger, the direct output of which is connected to the first, inputs of the first, second and seventh elements And, the output of the generator pulses is connected to the first one the house of the first element the first trigger is connected to the input I111I installation in 1 of the second trigger, the first inputs of the third and sixth elements And the second inputs of the fourth and fifth and seventh elements And, the output of the fourth element And is connected with S.vtory The main input of the reversible counter, the spreader, is connected to the negative electrode, the outputs of which are connected to the second diode of the device.