SU792574A1 - Synchronizing device - Google Patents

Description

(54) SYNCHRONIZED DEVICE

one

The invention relates to automation and computer technology and can be used in control systems, as well as in computer coordination with low-speed external devices.

A device for synchronizing pulses is known, which contains triggers AND matches elements ij.

The drawback of the device is the impossibility of correcting the synchronized pulses in frequency.

It is also known synchronization device, containing the elements of AND-NOT, triggers and inverter 2.

This device also does not correct the frequency of the synchronized pulses, therefore it cannot be used in matching computers and external devices with low speed.

The purpose of the invention is to expand the functional capabilities of the synchronization device, which is to provide the possibility of matching different speed devices.

The goal is achieved in that the synchro-25 kiziruyuschy device containing the first trigger and successively connected inverter, the first AND-NOT element, the second trigger, the second and third AND-NOT elements, and the input of the inverter is co-30

It is united with the second input of the second NAND element; the NAND element and the counter are additionally inputted; the output of the second trigger, the zeroing input of the counter and one of the inputs of the additional NAND element, the other input of which is connected to the input of the inverter, and the inverse outputs of the first trigger and the counter are connected respectively to the third input the second element NAND and zero input of the second trigger.

The drawing shows a block diagram of the device.

The synchronizing device contains an inverter 1, elements AND-HE 2, 3 4, 5, triggers 6.7, counter 8, bus

9 synchronized pulses 9, bus

10-stroke pulses, and the output bus 11.

The synchronization device operates as follows.

Claims (2)

When a synchronized pulse arrives on bus 9, for example, at the moment of a pulse on bus 10, the output of the AND-HE element 2 appears only after the end of the clock pulse, since a negative signal from inverter 1 blocks the signal from passing through - NOT 2. At the end of the passage of the clock pulse, the positive voltage from the output of the inverter 1 is applied to the element AND NOT 2, and then from its output to the single input of trigger b and sets it to the single state. At the moment when the next clock pulse appears, an output signal is generated at the output of the NAND 3 element (bus 11), the duration of which is equal to the duration of the clock pulse. At the same time, a positive voltage drop from the single output of trigger b gives permission for the passage of so-called pulses through the AND-HE element 5 to the counting input of counter 8 with a given conversion factor K. The first clock pulse from the output of the AND-HE element 5 sets the output of the first bit the counter 8 is a positive potential, which is fed to one of the inputs of the element AND-NO 4, the other input j oToporo receives an output pulse from the output of the element AND-NOT 3 and with its falling edge sets trigger 7 to one state. The zero potential from the inverse output of the trigger 7 blocks further passage of the clock pulses through the I-H 3 element to the bus 11. After the passage of the K clock pulses at the inverse output of the K-th digit of the counter 8, a negative voltage drop appears sets trigger 6 to zero. The zero potential from the single output of trigger 6 blocks the further passage of clock pulses through the AND-HE elements 3 and 5, and also flushes trigger 7 and counter 8. Thus, the device is set to its initial state and ready for receiving the next synchronized pulse. If the next synchronized impulse is scanned on bus 9 before the moment of filling the counter 8, then this impulse is transmitted. Thus, the condition F is applied to the frequency of the output signal — the cycle I to where K is the coefficient of recalculation of the counter 8, which is chosen from the required operating conditions Ugj. ftbix slax This device allows you to eliminate information distortion in low-speed external devices that occurs when triggering pulses are received with a frequency exceeding the required trigger frequency of these devices that do not have a start-up lock at the time of the external device response. This increases the accuracy of the correct operation of external devices. At the same time, the use of this device in systems with an electronic computer makes it possible to simplify the driver software of an electronic computer (external device maintenance program) by eliminating subroutines that provide waiting for the external device to operate, which increases the efficiency of using computer time. Claims of the invention: A synchronization device comprising a first trigger and an inverter connected in series, a first NAND element, a second trigger, a second and a third NAND element, the inverter input being connected to a second input of the NAND element, characterized in that functionality, it is additionally introduced in series connected element AND-NOT and the counter, the output of the first bit of which is connected to the second input of the third element AND-NOT, the output of which is connected to the single input of the first three gera, the zero input of which is connected to the output of the second trigger, the zeroing input of the counter and one of the inputs of the additional NAND element, the other input of which is connected to the input of the inverter, and the inverse outputs of the first trigger and the counter are connected respectively to the third input of the second AND-NOT match and zero input of the second trigger. Sources of information taken into account during the examination 1. USSR author's certificate No. 515267, cl. H 03 K 5/13, 1974. 2. USSR author's certificate number 464070, cl. H 03 K 5/13, 1973. WITH to llJ ±