SU842792A1 - Number comparing device - Google Patents

Description

The invention relates to automation and computer technology and can be used in automatic calibration facilities.

It is known a device for comparing numbers containing counters, elements OR, AND-NOT, in which an additional code of the minimum number is entered into one of the counters, the monitored sequence pulses in the form of a serial binary code go to one of the input buses, the other counter and a decoder analyze the difference accounts 1.

The disadvantage of this device is its complexity.

The closest to the present invention is a comparator device containing a generator, counters, a trigger-relay trigger, AND circuits, a polarity change circuit, a signal forming circuit for finding a number in and out of the interval, the trigger output of the left end of the interval being connected to the key input the circuit and through the delay element - with the input of the signal shaping circuit on finding the number to the left of the interval, the output of the number register is connected to the input of the key circuit and in parallel, through the inverter and the delay element, respectively, with the input of the form circuit of a signal of finding the number on the interval, the output of which is connected to the input of the signal generating circuit of finding the number to the left and to the input slot of finding signal generating circuit of the right slot right output register

The 0 end of the interval is connected to the input of the memory element, the negative output of which is connected to the input of the formation circuit of the signal for finding the number to the right of the interval, and the zero output is connected fo with the input of the formation circuit of the signal for finding the number in the interval. .- Nedotatok known device also its complexity.

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The purpose of the invention is to simplify the device.

Claims (2)

The goal is achieved by the fact that in the device for comparing numbers, the pulse generator contains 5 ows, counters, triggers, AND, AND-NOT elements, the output of the pulse generator is connected to the first input of the And element, the output of which is connected to in,. | to the formaldia inputs of the first, second, and third counters, and the installation inputs to the zero state of the counters and flip-flops are connected to the device initial installation bus; the overflow outputs of the first, second, and third counters are connected to the installation inputs of the first, Etori, and third installation triggers, respectively, the direct outputs of the triggers are connected to the inputs of the first element —IN — NO, the output of which is connected to the second input of the X element by the first output bus of the device; the inverse outputs of the first and third trigger The first and second outputs of the second trigger are connected to the inputs of the second NAND element, the output of which is connected to the third input of the element and to the second output bus of the device, the first outputs of the first and third triggers, and the inverse output of the second trigger, are connected to the inputs of the third the NAND element whose output is connected to the third output bus of the device and to the fourth input of the AND element, the fifth input of which is connected to the control bus of the device. The drawing shows the block diagram of the device. The device contains a generator of 1 pulses, element 2, counters 35, triggers 6-8, elements AND-HE 9-11, output buses 12-14, control bus 15, bus 16 of the initial installation. The device works as follows. Before starting the comparison, all the counters and triggers are set to the zero state. Then, the lower, upper values of the interval and the comparing binary number are entered into the corresponding counters 3-5. The input of the element I2 receives a signal. The commencement of comparison over the control bus 15. The counting pulses from the generator 1 through the element And 2 begin to flow to the counting inputs of the counters 3-5. Depending on the numbers recorded in the counters, the counters are filled in parallel. In this case the following cases are possible. If the binary number to be compared is in the interval, then the first is filled with counter 5, which, when going through O, will flip the trigger. 8 into a single state, with a high potential appearing at the third input of the NAND element 9. Then, triggers 7 and 6 are thrown. All the inputs of the AND NONE 9 element will have high potentials. This leads to a change in the potential at the output of the element AND-NOT 9 and the input of the element AND 2. Counting pulses no longer arrive at the inputs of counters 3-5, and the zero potential on the output bus 12 signals that the compared value A is in the specified interval (). If the compared number A is less than the Lower Tolerance, then the first counter is filled with 5, transferring trigger 8 to one state, then counter 3 is filled up and resetting trigger 6, with high potentials at the inputs of the AND-NE element 11 and low counting pulses cease to flow through an AND 2 element at the inputs of counters 3-5. On the output bus 14, a low potential indicates that the compared value is less than the lower tolerance value (and B). in the case when the compared value is greater than the upper tolerance value, then the first counter 4 overflows and the first trigger 7 is activated, all potentials of the AND-NE element 10 have high potentials, and the zero potential on the output bus 13 indicates that the compared value is greater upper permissible value (and c). Using the proposed device to compare numbers improves the authenticity of the calculation and simplifies the circuit design. The invention includes a device for comparing numbers, containing a pulse generator, counters, triggers, AND, AND-NOT elements, the output of the pulse generator connected to the first input of the AND element, the Output of which is connected to the information inputs of the first, second and third counters, and the installation inputs in The zero state of the counters and flip-flops is connected to the device initial installation bus, so that, for the sake of simplicity, in it the overflow outputs of the first, second and third counters are connected to the installation inputs in one The state of the first, second, and third flip-flops, respectively, direct outputs of the flip-flops are connected to the inputs of the first NAND element, the output of which is connected to the second input of the And element and to the first output bus of the device, inverse outputs of the first and third triggers, and direct output of the second the trigger is connected to the inputs of the second NAND element, the output of which is connected to the third input of the AND element and to the second output bus of the device, the direct outputs of the first and third triggers and the inverse output of the second trigger are connected to the inputs the third element NAND, the output of which is connected to the third output bus of the device and to the fourth input of the element And, the FIFTH input of which is connected to the device control bus. Sources of information taken into account in the examination USSR certificate 06 F 7/04, 1976. USSR certificate 06 F 7/00, 1971 IS   li-