SU834940A2 - Frequency-controllable pulse generator - Google Patents

Description

The invention relates to pulse generators and can be used as a master oscillator in blocks of "synchronization of electronic computers and various automation devices.

According to the main auth. No. 744917 is a known frequency controlled pulse generator, containing AND elements, OR element, delay line, two control triggers, a counter and a register ij

The disadvantages of the generator were limited functional possibilities, since the duration of the generated pulses is constant and cannot be changed.

The purpose of the invention is to expand the functionality of the generator.

The goal is achieved by the fact that the generator, contains the AND elements, the OR element, the ZadroKki line and the register, and the information record entry. which is connected to the auxiliary code of the register read input is connected to the output of the support line, the outputs of the first and third electrons, and connected to the inputs of the OR element, two triggers and a counter, the installation input — of which

connected to the output of the register, and the subtracting input of the counter with the output of the second and one input of the third And elements, the other input of which is connected to the direct output of the first counter of the counter, the inverse outputs of all the following, which bits are connected to the remaining inputs of the third And element , the output of the first element I is connected to the counting inputs of the control triggers, and the installation input of the first trigger is connected to the start bus, the outputs of the first and second triggers are connected respectively to the first inputs of the first and second elements And the second inputs of which are connected to the pulse bus of the reference frequency, and the output of the OR element is connected to the input of the delay line, the additional trigger, the AND element, the counter and the register, the information recording input of which is connected to the pulse duration code bus, are read input connected to the read input the main register, the output is connected to the input, the installation of an additional counter, the subtracting input of which is connected to the subtracting input of the main counter and one of the inputs of the additional element AND, the other inputs of which are connected to the direct output of the first bit and inverse outputs of all subsequent bits of the additional counter, and the output is connected to the counting input of the additional trigger, the installation input of which is connected to the output of the OR element, and the output is connected to the output bus. The drawing shows the diagram of the proposed device. The device contains AND 13 elements, an OR 4 element, a delay line 5, a register 6, information recording input of which is connected to the N bus, a code, and a read input with the output of the delay line 5. The outputs of the And 1 and 3 elements are connected with the inputs of the OR element 4. The device also includes a counter 7, the installation input of which is connected to the output of the register b, and the subtractive input - to the output of the And 2 element and the first input of the And. 3 element, the second the input of which is connected to the direct output of the first discharge of the counter 7. The inverse outputs of all subsequent bits of the counter 7 are connected to the remaining inputs of the And 3 element, while the output of the And 1 element is connected to the counting inputs of the trigger 8 and 9, and the trigger input 8 is connected to the start bus. The outputs of the flip-flops 8 and 9 are connected respectively to the first inputs of the elements I 1 and 2, the second inputs of which are connected to the pulse bus of the reference frequency. The output of the element OR 4 is connected to the input of the delay line 5 and to the installation input of the trigger 10, the counting input of which is connected to the output of the AND 11 element, the first input of the AND 11 element is connected to the subtractive input of the counter 12 and to the echo travel of the AND 2 element, and the second input with the direct output of the first discharge of the counter 12, the inverse outputs of the subsequent bits of which are connected to the remaining inputs of the element 11. In addition, the device contains a register 13, the input of the information recording which is connected to the bus Cd. code, the read input is with the read input of register b, and the output is connected to the installation input of the counter 12, the output of the trigger 10 is connected to the output bus of the device. The device works in the following way. Before work triggers 8 10., Counters 7 and 12, registers b and 13 are set to zero. At the outputs of the flip-flops 8 and 9, low potentials are established that prevent the outputs of the elements I and 1 and 2 of the pulses of the reference frequency supplied to the bus of the pulses of the reference frequency. On the N and N buses, the codes receive the codes of the N and Yd numbers, specifying the follow-up period and the duration of the generator pulses on the output bus, respectively. The codes of the numbers N and N are written in registers b and 13, respectively. By the Start command arriving at the start bus, trigger 8 is set. in the state opened by the first input element AND 1. Then the closest in time to the Start command the pulse of the reference frequency passes to the input of the element FROM, from the output of the element AND 1 through the element AND 3 to the input of the trigger 10, setting it to the state, and , to the input of delay line 5, where it is delayed by a time equal to ty,. From the output of the delay line 5, the pulse arrives at the readout inputs of registers 6 and 13. From register 6 to counter 7, the code of number N is entered, from register 13 to counter 12 by the code of number. The first pass through the element And 1 impulse of the reference frequency also enters the counting inputs of the trigger 8 and 9 and on the trailing edge translates the trigger 8 to the state O, and the trigger 9 into the state, At this, the element 1 1 closes and the element And 2 opens , passes all subsequent pulses of the reference frequency to the subtracting inputs of counters 7 and 12 and the first inputs of the And 3 and 11 elements. The pulses of the reference frequency to the subtracting inputs of counters 7 and 12, subtract 1 from their contents one at a time. When the contents of counter 12 becomes one, i.e. its subtractive input is fed N. pulses of the reference frequency, high potentials are set on the outputs of all the bits of the counter 12, the element 11 is opened. the pulse passes through the element 11 on the counting input of the additional trigger 10, transferring it to the state O. At the output of the trigger 10, a pulse is formed, the duration of which is defined. is made by the contents of register 13. At the same time, the N, 2nd pulse on the falling edge subtracts 12 units from the contents of the additional counter, making it zero. After some time, the contents of counter 7 also become equal to one, i.e. on its subtraction. input enters the pulses of the reference frequency. At the outlets of all the rows of the counter 7, high potentials are set, the And 3 element opens. N -, - th pulse passes through the element And 3, the element OR 4 and enters the input of the installation of the trigger 10, its transfer to the state H, and the input of the line 5 of the delay; At the same time. N., - th pulse on the falling edge, subtracts from the contents of the counter 7 unit, making it equal to zero. From the output of the delay line 5, the pulse arrives at the readout inputs of registers b and 13 and, if the information is recorded in registers b and 13,

has not changed, the process is periodically repeated. At intervals of time determined by the number N-i, pulses are generated on the output bus, the duration of which is determined by the number N-X. If other numbers are recorded in registers b and 13, the next pulse appears on the output bus after a period of time and with a duration determined by the new numbers. To avoid the simultaneous arrival of the Nth pulse on the subtractive inputs of counters 7 and 12 and the arrival of information from registers b and 13 to the inputs of the installation of counters 7 and 12, the delay time of the delay line 5 is selected from the condition

. ,,

rfte (5 - delay line delay time

 - pulse duration reference frequency; Ta - the period of the pulse

reference frequency. For convenience of working with the generator, it is desirable that the pulse period of the reference frequency be a multiple of the time unit and, for example, 1 µs or 1s. In this case, the numbers N and N; are equal to the specified follow-up period and pulse duration in selected time units and can be set without prior scaling.

Thus, the proposed device in comparison with the known

by introducing a trigger and an And element, i, the register a and the counter has wider functionality, which is expressed in the ability to control the duration of the generated pulses.

Claims (1)

1. USSR author's certificate No. 744917, cl. H 03 L 7/00, 08.29.78. Lg