SU622172A1 - Dynamic storage - Google Patents

Description

VA, the input of the additional counter is connected via an additional key to the output of the pulse generator. The control input of the additional counter is connected to the output of the additional trigger, the output of the comparison circuit is connected to the output of the device, the "Reset Additional Counter" bus and to the second input of the OR element.

The drawing shows a block diagram of the proposed device.

The device contains a counter 1 (pulses), the input of which is connected to the output of key 2. One of the inputs of key 2 is connected to the output of the generator 3 pulses, and the second, control, input - to the output of trigger 4, in which one of the inputs is connected to the output of counter .1, and the second input — with the device input 5, a length of “Reset counter 1 and one of the inputs of the element OR 6, the second input of which is connected to the output of the comparison circuit 7, which is the output of the device. The device is equipped with annular registers 8, the shifting buses of which are paralleled and connected to the output of the element OR 6, the inputs are connected to the corresponding bits of counter 1, and the outputs are connected to one of the inputs of the circuit 7, the other inputs of which are connected to the corresponding bits of the additional counter 9. The reset bus of counter 9 is connected to the output of circuit 7, and the output of counter

9 is connected to the input of the additional trigger 10, the other input of which is connected to the input 11 of the pulse feed start device of the series. Trigger output

10 is connected to the control input of the auxiliary key 12, the other input of which is connected to the output of the generator 3 pulses, and the output to the input of the counter 9.

The operation of the device begins with the supply to the input 5 of a series of pulses, to be memorized. The first impulse of this series through the element OR 6 advances information in registers 8 to the unit, resets to counter 0, and translates trigger 4 into one. Trigger 4 permits the generator 3 to pass the counter 1 input. With the arrival of the next pulse, the code number generator pulses 3 for the first interval between pulses of a series are transmitted from counter 1 to the first bits of registers 8, information in registers is advanced by one, and counter 1 is prepared for a new pulse count of generator 3.

With the arrival of the third impulse of the series, the data of counter 1 is again recorded in registers 8. This happens until the end of the last impulse of the memorized series, after which the counter receives a certain number of impulses of generator 3 exceeding the number of pulses in the maximum memorized interval, which leads to the issuance of 1 impulse returning the trigger 4 to the zero state. As a result, the trigger 4 closes the key 2 and the supply of pulses to the input of the counter 1 is stopped.

The repetition of a series of pulses starts from the moment the starting pulse is applied to input I. This pulse converts trigger 10 into a single state, key 12 is opened, and generator 3 pulses start to flow to counter 9 input. Counter 9 counts generator 3 pulses until the code on the counter does not compare with the code formed by the last bits of the registers 8, after which the circuit 7 is activated, the first output pulse appears, which resets the counter 9 to zero and advances the unit recorded in p through the element OR 6 8 Trunk information.

Counter 9 starts counting generator 3, which continues until the counter codes are equal and the last bits of the registers 8. At the moment of equality, circuit 7 outputs the second pulse to the device output, performs the next reset of counter 9 and further advances the information in registers 8. The counting and issuing of output impuls occurs before

until both output registers 8 have reached the end code of the recorded series, then counter 9, by dialing the corresponding number, gives out a pulse, tilting the trigger 10 to the zero state. Trigger 10

closes key 12, which stops the supply of pulses from generator 3 to the input of counter 9. This completes the cycle of reproduction of a series of pulses recorded in registers.

A new cycle begins with the filing of a new starting pulse at the input of trigger 10. Key 12 is reopened, and counter 9 produces a pulse count to the value

the code of the end of the series, after which the circuit 7 forms the first pulse of the next series and the reproduction cycle repeats. Thanks to the closed registers 8, you can play the recorded signals

arbitrarily long.

To memorize and play a series with other periods between pulses, it is enough to submit a new series to input 5. This deletes the old ones.

code values and writing new to registers 8.

The invention is intended to work in the device vvada graphic information in a digital computer. It performs the functions of storing and cyclically reproducing large-scale pulses. The device is made on integrated circuits and has high reliability. It may also be used in radar information processing devices.

Claims (2)

Invention Formula Dynamic memory device containing a pulse generator, the output of which is connected to one of the key inputs, the second input of which is connected to the trigger output, one trigger input connected to one device input, the other to one of the counter outputs, the input of which is connected to the key, and A comparison circuit, characterized in that, in order to expand the field of application of the device, it contains ring registers, an OR element, an additional key, a trigger, and a counter connected by bit through a comparison circuit with ring outputs x registers, the shift inputs of which are connected to the output of the OR element, and controllers are connected to the counter, the output of the additional counter is connected to the first input of the additional trigger, the second input of which is connected to another input of the device, the input of the additional counter is connected via an additional switch to the output of the pulse generator , the control input of the additional counter is connected to the output of the additional trigger, the output of the comparison circuit is connected to the output of the Device, the bus "Reset of the additional counter and to the second by the input of the element OR. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 499676, cl. G PS 21/00, 1974. 2. USSR author's certificate No. 456357, cl. G NA 21/00, 1974.