SU1376243A1 - Binary code-to-time interval converter - Google Patents

Abstract

The invention relates to a computational technique, namely, information converting devices, and can be used in computer-aided automation systems. The invention allows the beginning and end of the time interval to be rigidly linked to the cutoff of clock pulses, which provides increasing the accuracy of the conversion. The binary code converter in the time interval contains two flip-flops 1 and 2, a generator of 3 pulses, a block of 4 registers, two counters 5 and 8 of a pulse element AND 6, an element of IS-NOT 7, two Owner 9 and 10 pulses and shaper I1 code sequences. 2 Il.

Description

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The invention relates to computing technology, namely, information conversion devices, and can be used in computer-aided automation systems.

The aim of the invention is to improve the accuracy of the conversion.

FIG. I shows the tO scheme of converting a binary code into a time interval; in fig. 2 - belt diagrams explaining the converter rata.

The binary code converter 15 to the time interval contains the first 1 and second 2 triggers, the generator 3 pulses, block 4 registers, the first counter 5 pulses, element 6, the element AND-7 7, the second counter 8 and 20 pulses, the first 9 and second 10 pulse shapers and shaper I1 code sequences. The converter (fig. 1) has control 12 and information 13 inputs and 25 output-14.

FIG. 2 is indicated: a - signal at the input 12 of the converter; b - the signal at the output of the generator 3; in - the signal at the output of the imaging unit 10; g - 30 signal at the output of the trigger 2; d - the signal at the output of the counter 8; e is the signal at the output of the imager 9; W - signal at the output of the counter 5; h - the signal at the output of the element AND-NOT 7; and - with the signal at the output of the trigger 1 and the output 14 of the Converter; K - signal at the output of the element And 6.

The converter of the moving code to the time interval works in the following way.

A pulse is applied to the input 12 of the poll, which is fed to the input of the trigger setup 2, allowing the change of: - the state of the latter under the influence of signals at the synchronization input, and to the input of the imaging unit 10.

The other input of the imaging unit 10 receives pulses from the output of the generator 3. At the output of the imaging device 10, a pulse is generated, the front of which coincides with the cut of the first pulse of the generator 3, and the cut - with the cut of the second pulse of the generator 3.

The pulse from the output of the former 10 is fed to the input of the installation of the counter 8. At the same time, the latter is reset and at its output a logical O appears. This signal is fed to

55

input shaper 9, preparing it to work.

Input 13 is supplied with serial pulsed binary soda via two communication lines in the form of direct and ing codes. The unit of code corresponds to the presence of a pulse on the communication line of the direct code and the absence of a pulse on the communication line of the inverse code, and to zero of the code - the absence of a pulse on the communication line of the direct code and the presence of a pulse on the communication line of the inverse code.

In the former 11, a series of pulses is formed at the first output, representing a total sequence of direct and pulses. inverse codes received via two communication lines to input 13, and the second output generates a direct code, and its pulse duration is extended to a pulse repetition period formed at the first output of driver M. You can implement such an algorithm for generating code sequences using parallel connected RS-flip-flops and an OR element, to the output of which a delay element is connected. Expansion of the pulse width of the direct Qbda and delay of the pulses at the first output ensures reliable writing of the code in block 4.

The counter 8 counts the number of pulses at the first output of the driver 11, i.e. the number of visitors Dov code. As soon as block 4 receives the last bit of the code, logical 1 appears at the output of counter 8, which carries the information that all bits of the code were recorded in block 4. This signal is fed to the input of shaper 9, at the output of which similarly to shaper 10, a pulse is formed, the front and the cut of this pulse being tied to the cut of the generator 3 pulses.

The pulse from the output of the imaging unit 9 is fed to the input of the record of the counter 5, while the parallel code generated at the outputs of block 4 is written to the counter 5, the output of which appears logical, which is fed to the R-code of the trigger 1 and NOT 7.

At the same time, the impulse from the output of the imager 9 turns over trigger 2 and logic 1 s.

its output is fed to the input element AND-NOT 7. Logical O from the output of the element AND-NOT 7 is fed to the S input of trigger 1 and turns it upside down, forming the front of the output time interval at output 14. Since the change in the state of trigger 1 occurs The pulse of the former 9, which coincides with the pulse of the generator 3, the front of the formed time interval is rigidly attached to the pulse of the generator 3.

Logical 1 from the output of trigger I is fed to the input of the element And 6,. Solving the passage of the pulses of the generator 3 through the elements And 6 and the input of the readout of the counter 5, the code recorded in the counter 5, begins to be read. As soon as the code is counted, a logical O appears at the output of the reversible counter 5, and this signal is generated by a slice of the generator pulse 3, which causes the counter 5 to be reset.

A logical O from the output of the reversible counter 5 is fed to the R-trigger input 1 and to the input of the element IS-NE 7. The output of the last logical 1 is triggered. The trigger 1 turns over and an output time interval 14 is cut. the state of the trigger 1 is connected to the cutoff of the pulse of the generator 3, causing the zeroing of the counter 5, the cut of the time interval being formed is rigidly attached to the cutoff of the pulse of the generator 3.

. Thus, at the output of the trigger 1, which is connected to the output 14, a pulse is generated, the duration of which is determined by the entered code.

Logic O from the output of trigger 1 is applied to the element And 6, prohibiting the passage of the pulses of the generator 3 through the element And 6 to the input subtraction

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Claims (1)

The invention Binary code converter in a time interval containing the first and second triggers, a pulse generator, a register block, the outputs of which are connected to the information inputs of the first pulse counter, the output of which is connected to the first input of the first trigger, the output of which is connected to the first input of the And element, characterized in that, in order to improve the accuracy of the conversion, the elements of the NAND, the second pulse counter, the pulse formers, the driver of the code sequences are introduced into the converter tey, the first output of which is connected to the first, Bbw control of the input of the register block and the first input of the second pulse counter, the output of which is connected to the first input of the first pulse generator, the output of which is identical to the first control input of the first pulse counter and the first input the second trigger, the output of the pulse generator is connected to the first input of the second pulse driver and to the second inputs of the first pulse driver and the element And, the output of which is connected to the second control input of the first counter impulses, the output of the second trigger is connected to the first input of the NAND element, the output of which is connected to the second input of the first trigger, the output of the second impulse generator is connected to the second input of the second pulse counter, the second input of the NID element is connected to the output of the first pulse counter, the second output the code sequence generator is connected to the second input of the register block, the second inputs of the second pulse shaper and the second trigger are combined and are the control input of the converter, the shaper input pa sequences and output of the first flip-flop are respectively an information input and output transducer. FIG. 2