SU1368957A1 - Device for shaping pulse sequences - Google Patents

Abstract

The invention can be used in multichannel digital information signaling devices over wired communication lines. The device contains a block of 2 And elements, a generator of 3 clock pulses, a block of 4 flip-flops, an element of OR 5, a block of 6 registers and a block of 9 controls. The reliability of the transmitted information (AND) is increased due to the fact that AND received during the operation of control unit 9 is not reset in block 4 of the trigger with a signal and in the next cycle of operation of control unit 9 is transmitted to the output of the device. At the same time, in the process of sending AND to the device output, only those triggers of block 4 of flip-flops are reset, from whose outputs the unit level was copied to block 6 of registers, and AND received during the transfer is transmitted to the output of the device in the next cycle. The description provides an example of the implementation of control block 9. 1 hp f-ly, 1 ill. sl 00 a 00 con

Description

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The invention relates to a pulse technique and can be used in multichannel digital information signal transmission devices over wired communication lines.

The purpose of the invention is to increase the reliability of the transmitted information.

The drawing shows a functional diagram of an apparatus for generating pulse sequences.

The device contains input bus 1, block 2 elements And, the generator 3 clock pulses, block 4 flip-flops element HJTli 5, block 6 registers, block 7 elements And, output bus 8, block 9 control, which contains the trigger 10, the counter 11 pulses, elements And 12-16, elements NOT 17 and 18, element OR 19, and the generator output

3-stroke pulses are connected to the second input of the control unit 9, the first output of which is connected to the second inputs of the block 2 of the elements I, the outputs of which are connected to the R-inputs of the block

4 triggers, the C inputs of which are device inputs, block outputs

And the flip-flops are connected to the D-inputs of a block of 6 registers and to the inputs of an element OR 5, the output of which is connected to the first input of the control block 9, the third output of which is connected to the C-inputs of the block of 6 registers, the outputs of which are connected to the first inputs of blocks 2 and 7 And, the outputs of the last are the outputs of the device, the second inputs of the block 7 of the elements And are connected to the second output of the control block 9, the first input of which is connected to the first input of the element And 12 the output of the latter is connected to the S input of the trigger 10, the inverse output of which is connected to R-in the house of the pulse counter 11, the C input of which is connected to the second input of the control unit 9, the first output of the latter is connected to the second input of the OR element 19 and the output of the AND 16 element, the third input of which is connected to the third output of the pulse counter 11, the second input of the And 13 elements and 14, the output of the latter is connected to the first input of the OR element 19, the output of which is connected to the second output of the control unit 9, the third output of which is connected to the inverted output of the AND element 15, the first input of which is connected to the first output of the pulse counter 11, the first input lementa and 14 and entrance

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He element 17, the inverse output of the latter is connected to the first input of the element AND 16, the second input of which is assembled; dinen with the inverse output of the element HE 18, whose input is connected to the second output of the pulse counter 11 pulses, the second input of the element And 15 and the first input of the element And 13, the inverse output of the latter is connected to the second input element And 12 and the R input of the trigger 10.

The device works as follows.

At the C-inputs of the input triggers of block 4, bus 1 receives impulses from the asynchronous flow, which set the unit level on the corresponding outputs of block 4 of triggers. In this case, the unit level passes through the OR 5 element at the first input of the AND 12 element, at the second input of which in the initial state there is a single level. The signal from the output of the element 12 goes to the S input of the trigger 10. At the inverse output of the trigger 10, a zero level appears that goes to the H input of the counter 11 and allows the latter to start counting the pulses from the generator 3. With the arrival of the third clock pulse a pulse triggered element And 19, the output of which generates a signal, arrives at the control C-inputs of registers of block 6, while the input information is rewritten from the output n of the input triggers of block 4 to the output hect of registers of the block 6, and goes to the first inputs of the corresponding n And lementov blocks 2 and 7.

With the arrival of the fourth clock pulse, the element AND 16 of the control block 9 is activated. The signal from the output of the element And 16 is fed to the second inputs of the elements of And block 2, which permits the passage of the signal to the R-inputs of the triggers of block 4, in which the received information, has brought the outputs of these triggers, while the outputs of the elements OR 5 and AND 12 is set to zero level. At the same time, the signal from the output of the element AND 16 through the element OR 19 of the control unit 9 is fed to the second inputs of the element. And block 7, ensuring the formation of output pulses at the outputs of the elements And block 7. With the arrival of the fifth clock pulse, the element And 14 of the control block 9, you

xofHOH the signal of which is supplied through the OR 19 element to continue the formation of output pulses at the outputs of the elements AND of block 7. The formation of output pulses stops with the arrival of the sixth clock pulse. At the same time, the sixth clock pulse triggers the element AND 1 3 of the control unit 9, the output signal of which resets the trigger 10, ensuring the reset of the counter 11 to the initial state. If the information from the code of block 4 flip-flops is rewritten into block 6 of registers, and the C-inputs of flip-flops of block 4, whose outputs have a zero level, receive pulses from the asynchronous flow, then the outputs of the corresponding triggers of flip-flops of block 4 are set to a single level. The trigger data is not reset to O, since the block 2 of the elements And does not allow the signal from the output of the element AND 1 6 of the control block 9 to the R-BXOs of the corresponding triggers of block 4, since its first inputs have a zero level. In this case, the output of the element OR 5 remains a single level. At the end of the sixth clock pulse, which sets the trigger 10 and the counter 11 to the initial position, from the output of the element 12 to the S input of the trigger 10 a single level is received, which takes the trigger 11 to the working state and the process of transmitting information to the output of the device received during the previous process, is repeated.

The device for forming pulse sequences allows to increase the reliability of the transmitted information due to the fact that the information received during the operation of the control block 9 is not reset in the trigger block A by a signal from the first output of the control block 9 and in the next cycle of the block operation 9, the control is transmitted to the output of the device. Since in the process of transmitting information

only those triggers of block 4 are reset to the output of the device, from whose outputs the unit level has been rewritten into block 6 of registers and the information

received during transmission, transmitted

Claims (2)

1. An apparatus for generating pulse sequences comprising 15 0 5, 5 .,. . „ U 0 five the triggers block, the register block and the first AND block, as well as the control block and the clock generator, the output of the clock generator are connected to the first input of the control block, the C input of each of the trigger blocks of the trigger block is connected to the corresponding input bus, the second inputs of the And block are connected to the first output of the control block, the second output of the control block is connected to the C inputs of the register block, which is because, in order to increase the reliability of the transmitted information , the second block of AND elements and the OR element are entered into it, while the outputs of the register block are connected to the first inputs of the second block of AND elements, the second inputs of which are connected to the third output of the control unit, the outputs of the second block of AND elements are connected to the R inputs of the trigger block, outputs which is connected to the inputs of the OR element, the output of which is connected to the second input of the control unit. 2. The device according to claim 1, characterized in that the 4to control unit contains a trigger, pulse counters, five AND elements, the first and second Hf elements, an OR element, and the R-input of the trigger is connected to the inverse output of the first And element, the first input of which connected to the input of the second element NOT, to the second input of the third element I, to the second output of the pulse counter, the third output of which is connected to the second inputs of the first, second and fourth elements I, the output of the latter connected to the third output of the control unit and to the second input of the PI element, P The first input of which is connected to the output of the second element I, the first input of which is connected to the input of the first element NOT, to the first output of the pulse counter and the first input of the third element I, the inverse output of which is connected to the second output of the control unit, the first output of the control unit is the output of the element OR, the inverse of the second element is NOT connected to the third input of the fourth element AND, the first input of which is connected to the inverse output of the first element NOT, vtc) the second input of the control unit is connected to the first input 51368957 6 the house of the first element, And, the second entrance and inverse output of which is connected to which is connected to the inverse output R-input of the pulse counter, C-input The first element, And, the output of the fifth ele-which is the first input of the AND block, is connected to the S-input of the trigger, as a control.