SU930626A1 - Pulse delay device - Google Patents

Pulse delay device Download PDF

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Publication number
SU930626A1
SU930626A1 SU803008497A SU3008497A SU930626A1 SU 930626 A1 SU930626 A1 SU 930626A1 SU 803008497 A SU803008497 A SU 803008497A SU 3008497 A SU3008497 A SU 3008497A SU 930626 A1 SU930626 A1 SU 930626A1
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SU
USSR - Soviet Union
Prior art keywords
counter
input
output
inputs
delay
Prior art date
Application number
SU803008497A
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Russian (ru)
Inventor
Повилас Петрович Кемешис
Статис Юргевич Норейка
Альгимантас Иполитович Рудженис
Original Assignee
Каунасский Политехнический Институт Им.Антанаса Снечкуса
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Priority to SU803008497A priority Critical patent/SU930626A1/en
Application granted granted Critical
Publication of SU930626A1 publication Critical patent/SU930626A1/en

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Description

(54) DEVICE FOR DELAYING PULSES
The invention relates to a pulse technology and can be used in modern communication technology, radio engineering, computer technology and other radio electronics, as well as in speech processing systems. A device for delaying pulses is known, which contains a clock generator; pulses, two counters, the first of which is connected to the code comparison circuit through a memory device, and the second directly, two controllable first and second triggers of the And element, respectively, the output of each of which is connected to the corresponding pulse counter, the third And element, whose inputs are connected with the corresponding one-bit outputs of the second counter, and the output with the single input of the first trigger, the generator output also connects the pulses to the free inputs of the first and second elements I. zero input p The first trigger, the single input of the second trigger, allowing the memory input, the reset input of the second counter are connected to the device input, and the reset input of the first counter is entered through the delay driver, while the output of the comparison circuit, the codes is connected to the reset input of the memory device and the zero input second trigger l. A disadvantage of the known device is that it does not operate only with periodic signals. A device for delaying pulses is known, comprising a clock pulse generator, two counters, a trigger controlled first element I. Its input is connected to a clock pulse generator output, a main delay driver whose input is connected to a device input, a single trigger input and a second counter reset input, the second element is And, the inputs are connected to the corresponding bit-wise counters of the counter, /1.epementoe And, bpok dubbing, the auxiliary delay generator, the output of which is connected With the zero input of the trigger and the fault input of the first counter, the output of the main delay shaper is connected to the input of the auxiliary delay shaper and with the enable input of the rewriter block whose inputs are connected to the corresponding bit ports of the first counter, and the outlets with the corresponding digit inputs of the second the counter, the inverse output of the last digit of the first counter is connected to the input of the first element I, whose course is connected to the inputs of both counters, the inputs of each of the P element This is connected to the corresponding output of the second counter. 2 The disadvantage of this device is the impossibility of forming a delay depending on the frequency of the following quasi-periodic sequence of pulses so that the delay time of the pulse is proportional to the preceding period. The purpose of the invention is to expand the functional capabilities of the device by providing a delay proportional to the previous period. The goal is achieved by that; that a pulse counter, containing a clock pulse generator, has a first counter, the aerial outputs of which are connected to the outputs of the rewriting unit, the outputs of which are connected to the corresponding setup inputs of the second counter, which by its outputs are connected to the inputs of the multi-input coincidence element, the control unit of the rewriter and reset, entered the frequency divider, which is connected to the output of the clock pulse generator, and the output trigger one input of which is connected to the output of the multi-input element The match is coincident, and the other is connected to the output of the control unit of the rewriting and reset unit, the counting input of the first counter is connected to the output of the frequency divider, and the counting input of the second counter to the output of the clock generator. The drawing shows a structural electrical circuit of the device. The device contains a generator of 1 so-called pulses, a divider 2 frequencies, an element 3 controlling the rewriting unit and a reset, the first counter 4, the rewriting block 5, the second counter 6, the multiple coincidence element 7, the trigger trigger 8. The outputs of the first counter 4 are connected to the installation inputs of the second the counter 6 is via rewriting block 5, which is controlled by the element 3. The counting input of the second counter 6 is connected to the output of the generator 1, and the counting input of the first counter 4 is connected to the output of the frequency divider 2. One input of the output trigger 8 is connected to the output of the control unit 3 rewriting unit and reset, and the other to the output of the multi-input matching element 7, the inputs of which are connected to the outputs of the second counter 6.. The device works as follows. The generator 1 clock pulses to generate pulses with a periodT. The counting input of the first counter 4 receives pulses with a period of T2 T K, where K -1 is the division factor of frequency divider 2. During time T, equal to the current period of the input quasi-periodic sequence, a certain integer number of pulses is sent to the count input of the first counter. In this case, the triggers of the first counter 4 receive a state characterizing a binary number proportional to the time interval T. On the leading edge of the next input pulse, the element 3 of the rewriter and reset control generates a short pulse that leads you. a trigger trigger 8 to the state O (the start of the delay) and allows code to be rewritten from the first counter 4 to the second counter 6, and the reverse code is rewritten to the second counter 6. After rewriting the code, the control block 3 rewriting element and reset resets the triggers of the first counter 4. After a certain time Tc, the second counter 6 goes into the final state and at the output of the multi-input coincidence element 7 a pulse appears that puts the trigger 8 into the state (end delays). Since the counting input of the second counter 6 receives impulses with a period T, then Tz MiT (T / T) X (T2 / K) TJ. It is seen that the delay time T for a given proportionality coefficient K depends on the time interval T between the input pulses, i.e. the system adjusts itself to the input signal. The proportionality factor can be changed.
by changing the division ratio of the frequency divide 2.
This implementation ycipoftcTa allowed ;; It does not receive a delay in the input quasi-periodic sequence, which depends on the input period, which is especially useful in speech signal processing systems, in particular, in peak-tone speech extraction systems, as this increases the accuracy of laziness.

Claims (2)

  1. Invention Formula
    The device is a pulse delay delay that contains a clock pulse generator, the first counter, the bit outputs of which are connected to the inputs of the rewriting unit connected by codes to the corresponding adjusting inputs of the second counter, which by its outputs is connected to the inputs of a multi-input switch 8
    coping, overwrite and reset block control element, that, in order to expand the functionality
    5 by providing a delay, about the legal previous period, a frequency divider is inserted into it, connected to the output of the clock generator, and an output trigger, one input which is connected to the multi-input matching element, and the other to the output of the rewrite control unit to reset . COM) with the counting input of the first counter connected to the output of the frequency divider $
    5 and the counting input of the second counter to the output of the clock pulse generator.
    Sources of information taken into account in the examination
    1. USSR author's certificate 0 No. 529554, cl. H 03 K 5/153,
    15.O4.75,
    2. USSR author's certificate number 738134, cl. H 03 K 5/153, 20.O3.78 (prototype).
  2. B) 1-8
    eight
SU803008497A 1980-11-26 1980-11-26 Pulse delay device SU930626A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU803008497A SU930626A1 (en) 1980-11-26 1980-11-26 Pulse delay device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU803008497A SU930626A1 (en) 1980-11-26 1980-11-26 Pulse delay device

Publications (1)

Publication Number Publication Date
SU930626A1 true SU930626A1 (en) 1982-05-23

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ID=20927654

Family Applications (1)

Application Number Title Priority Date Filing Date
SU803008497A SU930626A1 (en) 1980-11-26 1980-11-26 Pulse delay device

Country Status (1)

Country Link
SU (1) SU930626A1 (en)

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