SU1370750A1 - Clocking device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention, the increase in resolution, is achieved by forming separate output pulses, the duration of which is equal to the period of the clock frequency when the next one pulse appears at the moment of forming the result from the effect of the previous output pulse. To do this, an AND 4 element and the corresponding functional connections are additionally introduced into the device. The device also contains D-type triggers 1 and 5, switch 2, input bus 3, output bus 6, bus 7 clock pulses. Switch 2 is made on the logical element 2-ZI-2IL. The device has the ability to distinguish successive input pulses with an interval of less than the period of clock pulses, which increases its resolution. cl

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase the resolution due to the formation of separate output pulses, the duration of which is equal to the period of the clock frequency when a subsequent input pulse appears at the moment of forming the result from the effect of the previous output pulse.

The drawing shows an electrical functional diagram of a clock synchronization device.

The device contains the first trigger 1 (D-type), the inverse output of which is connected to its D-input and the first control input of the switch 2 (element 2-ZI-2IPI), the first information input of which is connected to the input bus 3, the output - with The C-input of the first trigger 1, the direct output of which is connected to the second control input of the switch 2 and the first input of the And 4 element, the output of which is connected to the D input of the second trigger 5 (D-type), direct; The t of which is connected to the output bus 6, the inverse output to the second input of the element 4 and the third control input of the switch 2, the second information input of which is connected to the C input of the second trigger and the bus 7 clock pulses.

The device works as follows.

In the initial state, the triggers 1 and 5 are in the zero state (the setting means in the initial state are not shown), and according to the signals coming from the direct and inverse outputs of the trigger 1, the bus 3 through the switch 2 is connected to С -the input of the trigger 1, on the D-input of this trigger there is a single signal.

By a slice (transition from 1 to O) of the signal received via bus 3 via switch 2 to the C input of the trigger 1, the latter is set to one and a single signal appears at its direct output and zero on the inverse.

As a result, a zero signal arrives at the D-input of the trigger, and bus 7 is connected to the C-input of the trigger 1.

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Since trigger 5 is in the zero state, there is a single signal at its inverse output that allows bus 7 to connect to the C input of trigger 1 and transfer information from the forward trigger output to D input of trigger 5, i.e. The D-input of the trigger 5 receives a single signal from the direct output of the trichter 1.

Trigger 5 is switched over the next clock pulse received on bus 7, and the front of the pulse on bus 6 is formed at its forward output. At the same time, the zero signal from the inverse output of trigger 5 prohibits the transmission of information to the D input of this trigger from the pr The output of trigger 1, and also prohibits the connection of bus 7 to the C input of trigger 1. In addition, a cut of the same pulse on bus 7 resets Tritter 1 and, in accordance with signals from its forward and inverse outputs, to C input of the trigger 1 connects h Through switch 2 bus 3. By cutting the next clock pulse coming through bus 7, trigger 5 is reset to its original state (zero) and a cut of output pulse on bus 6 is formed. A single signal from the inverted output of trigger 5 arriving at the input of the And 4 element , permits the transfer of information from the direct output of the trigger 1 to the D input of the trigger 5.

If during the formation of the output pulse, the bus 6 (when the tripler 5 is set to one) receives the next signal on the bus 3 via switch 2 to the C input of the trigger 1, the latter is set to one. In this case, a zero signal is generated at its inverse output, in accordance with which the bus 3 is disconnected from the C input of the trigger 1.

At this point in time, the inverse output of the trigger 5 also contains a zero signal, which blocks the connection to the C input of the trigger 1 of the bus 7. As a result, after the cutoff

the next clock pulse trigger 1 retains its state, and the trigger 5 is reset to its original state and the formation of the first output pulse on the bus 6 ends

is. At the inverse output of flip-flop 5, a single signal appears, which allows the transfer of information from the direct output of flip-flop 1 through element 4 to the D-input of flip-flop 5, as well as connection to the C-input of flip-flop 1 of bus 7. By slice the next clock pulse trigger 1 is reset, and trigger 5 is set to one. A forward output pulse is generated by the next output impulse arriving at bus 6,

Further operation of the device is carried out as described.

Claims (1)

Invention Formula A clock synchronization device containing the first trigger, D-input ko70750 Secondly, it is connected to its inverse output and to the first control input of the switch, the first information input f with the input bus, the output to the C input the first trigger, the direct output of which is connected to the second control input of the switch, the second information input of which is connected to the clock pulse width and the C input of the second trigger, the direct output of which is connected to the output bus, due to the fact that, in order to increase the resolving method), an element I was entered into it, the output of which is connected to the D input of the second trigger, The switch input, the third control input of which is connected to the second input of the AND element and the inverse output of the second trigger.