SU1706027A1 - Pulse duration selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used to select pulses of a given duration. The purpose of the invention is to provide the possibility of restoring on the output tires both pulses, the duration of which is equal beyond a given threshold, and pulses that exceed a predetermined threshold — achieved by introducing the first and second triggers 4 and 5 and the second output bus 9. The device also contains 1 clock generator pulses, shift register 2, the element OR 3, the element AND 6, the input bus 7 and the first output bus 8, 4 Il.

Description

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The invention relates to a pulse technique and can be used for the selection of pulses of a given duration.

The purpose of the invention is to provide the possibility of restoring on the output tires both pulses, the duration of which is equal to a given threshold, and pulses, the duration of which exceeds a predetermined threshold.

Figure 1 shows the structural electrical circuit of the device; FIGS. 2-4 are timing diagrams explaining his work.

The device (figure 1) contains a generator 1 clock pulses, the output of which is connected to the clock input of the shift register 2, the element OR 3, the first input of which is connected to the output of the first trigger 4, and the output - to the D input of the trigger 5. The first and second outputs trigger 2 is connected respectively to the first and second straight inputs of the element And b, the information input to the input bus 7, and the third output to the first output bus 8 and the second input of the element OR 3. The output of the trigger 4 is connected to the second output bus 9, R -input - with the first output of register 2, and S-input - with output element b and b, the inverse input of which is connected to the input bus 7 and the third input of the element OR 3. The reset input of the register 2 is connected to the inverse output of the trigger 5, the C input of which is connected to the output of the generator 1.

2-4, the digital indications of the time diagrams correspond to the numbers of the registers and tires in FIG.

The selector works as follows.

Initially, shift register 2 and triggers 4. 5 are in the zero state. The input signal is fed to the information input of the shift register 2 and through the OR element 3 to the D input of the trigger 5. From the output of the trigger 5, the fault potential is removed to the reset input of the shift register 2.

When the input signal arrives at the information input of the shift register 2, its bits in series, beginning with the first one, level 1 is recorded, since the synchronizing impulse is constantly blunt on the multifunction input of the shift register 2 :. providing the shift inforg-ec. and from the previous bit to the next ./

Selem MI set up the selection of pulses. , g - - - which are greater than the value of N; 7 NT, where N is the resolution, character 1. -. pooog selection; T is the pulse period of the clock pulse generator 1, and extracts the pulses at the third output of the shift register 2.

In addition, the same selector structure

allocates (output of the first flip-flop 4) pulses of a given duration ri - nT, where n is the corresponding register bit of shift 2, with m 1 l.

If the duration of the input signal

less than the duration r and does not coincide with the given duration t, then at the end of the input pulse the signal with the level O from the input of the selector through the element OR 3 is entered into the trigger 5, the signal from the inverse

the output of which the shift input register 2 is reset is reset. If the duration of the input signal meets the condition ri NT, then with the appearance of level 2 in the Nth digit of the de register 2,

through the element OR 3, the potential of the level G at its output keeps trigger 10 in the previous state until the end of the pulse on the bus 8 of the selector.

If the input signal corresponds to a given duration of the PT, then with the appearance of level 1 in the nth digit of register 2, level 1 is retained at the inverse output of the (n + 1) –th digit. If between clock pulses from the generator 1 clock pulses input

the signal ends, i.e. corresponds to the duration of the pT, then the zero potential from the input bus 7, coming to the inverse input of the element 6, causes it to trigger and, accordingly, the installation of the trigger 4,

the potential of level 1 from the output of which through the OR element 3 appears at the D input of the trigger 5. At the same time, the short-term appearance at the D input of the trigger of level 5 O does not trigger it, since

walks between the clocking pulses of

nerator 1.

The signal from the output of the trigger 4 is allocated to the second output bus 9 of the selector, and through the element OR 3 and the trigger 5 prevents the reset of the register 2 before the termination of the signal on the bus 9 and the occurrence of the level O in the nth level of the register 2 shift returns trigger 4 to its original state.

Thus, the proposed selector selects two types of signals and generates signals of similar duration on the output buses 8 and 9.

Claims (1)

Claims of the Pulse Width Selector, comprising a clock pulse generator, the output of which is connected to the clock input of the shift register, the information input of which is connected to the input bus and the inverse input of the AND element, the first and second direct inputs of which are connected respectively to the first and second outputs of the shift register, and also the OR element and the first output bus, different in that. in order to enable the output tires to recover not only pulses whose duration is equal to a predetermined threshold, but also pulses whose duration exceeds a predetermined threshold, the first and second triggers and the second output bus, which connected to the first input of the OR element and to the output of the first trigger, the S input of which is connected to the output of the AND element, a R input to the first output of the shift register, the third output of which is connected to the first output bus and to the second input of the OR element, the first input which is connected to the input bus, and the output - to the D-input of the second trigger, the C-input of which is connected to the pulse generator of the clock pulses, and the inverse output to the reset input of the shift register.