SU1177910A1 - Device for generating quaternary-coded sequences - Google Patents

Description

The invention relates to a generator of broadband noise-like signals and can be used in radiolocation, radio navigation, radio communications, synchronization systems 5 and other radio engineering systems for constructing generators of quaternally-coded sequences.

The purpose of the invention is to improve the accuracy by improving the correlation properties of the formed sequences.

The drawing shows a block diagram of a device for generating four-coded sequences.

A device for generating quaternally coded sequences contains a generator of 1 clock

, pulses, binary (t-raz row count-. 20 chik 2, modulator 3, K & -trigger 4 _} n-bit parallel register 5, element OR-NOT 6, adders 7 ^ -7 _n modulo two, elements AND 88 _P.

A device for the formation of 25-encoded-encoded sequences works as follows.

In the initial state CL-trigger 4 is in the zero state, i.e. at its output - zero potential. Therefore, at the output of the element OR NOT 6, there is a single (high) potential that provides the initial (zero) state of the K-bit counter 2, i.e. on the outputs of all his l. Discharges - zero state, despite the fact that at its output there are clock pulses.

In addition, the prohibition of 40 state transitions of the digits of the νι-bit parallel register 5 is provided, since its clock input is also connected to the output of the OR-NOT 6 element, even if its state coding inputs 45 change state. The same output of the element OR NOT 6 keeps the modulator 3 in the off state. Since the outputs of the binary are n-times-. row counter 2 are zero states, and they are connected to the corresponding inputs of the AND 8-, - 3 ^ elements, then regardless of the states at the outputs of the η-bit parallel register 5 and adders 7. - 7 _П , at the outputs of the 55 And 8 elements ^ - 8 _n , and therefore at the inputs of the first adder 7 modulo: two zero potentials. Consequently, at the output of the first adder 7 modulo two, the zero state is held. So on the information and control inputs of the modulator 3 are also zero states.

When a start impulse device arrives at the launch input

~ £ ~ ⁺ % '

where - the clock frequency of the generator of clock pulses;

B _o - the delay time of the trigger short-trigger 4,

it is gated by the clock pulse of the generator G of clock pulses and simultaneously with the front of this clock pulse of the KZ-flip-flop 4 turns into a single state. At the same time, at the output of the element OR NOT 6, a level difference from one to zero is formed, which ensures the installation of a zero level at the input of the installation to the zero state K of a binary n-bit counter 2; write to the p-bit parallel register 5 of its input state, which was on the coding inputs at the time of gating the trigger pulse, the inclusion of the modulator 3.

I

Since the zero potential input to the binary digit counter η-2 is both permissive account, with the advent of the next clock pulse generator 1 of clock pulses of the binary state of η-bit counter 2 will vary with the frequency £ _t sampling clock. Exactly through 2 ¹ clock cycles, at the ηth output of the binary

The η-bit counter 2 will have a single potential, which will return to the initial (zero) state of the short-circuit trigger 4. But the zero state at the output of the element OR NOT 6 will not disappear, so. as the unit state of the ηth digit of the binary η-bit counter 2 will now be at another input of the OR-NOT 6 element exactly Σ * '"' cycles.

Thus, at the output of the OR-NOT 6 element, the zero state is exactly 2 ¹⁰ clocks from the moment of gating the starting pulse at the device start input. At the moment of returning the η-bit of the binary p-bit counter 2 to the zero state, is the input of the OR-NOT 6 element

3

1177910 4

there will be zero states, which corresponds to the return of the device to its original state.

From the launch device 5 determined gating trigger pulse to trigger input γοτρθήοτΒ8 _ί η-bit binary counter 2 is in dynamic (.schetnom) able to exactly 2 clock cycles ^and the generator 1 of clock pulses, whereupon 10

automatically the device will return to the original state described above.

The sign for η terms, each of which is a sequence of 2 ⁿ elements, explains the purpose of the first adder 7 ^ modulo two, the output of which must be formed given-code. Each term of the inputs of the first adder 7 ^ modulo two is the result of ANDing two .kodovyh sequences, which implies the need to incorporate at the inputs of the first adder 7 _A modulo two ^ 5

elements And 8 ^ - 8 _And . One of the input code sequences of the 3 ~ th element I (^ = 1,2, .., n) is the sequence a '*. which is formed on s ~ m output 30

binary η-bit counter 2, when the latter is in a dynamic (counting) state. Therefore, the first input,] of the first element And is connected directly to the ^ -th digit of the binary 35 η-bit counter 2. Another input code sequence arriving at the second input of the 3rd element And is the sequence formed on (^ -1 ) m, 40 i.e. the previous one, the discharge of a binary η-bit counter 2, but preliminarily summed modulo two and 3 ~ 3 bits of the binary inverse. The η-bit representation of the number of the generated sequence x |. Consequently, at the second input of the 3 th element, it is necessary to turn on the modulo two adder, the first input of which receives a sequence from the output (.] -!) Of the second digit of the binary n-bit counter 2, and the second input has the value η discharge, η-bit register 5, corresponding to the state of its memory element (^ flip-flop), which is determined by the moment of triggering the trigger pulse on

device startup input. The state of the memory elements of the η-bit parallel register 5 in the dynamic mode of operation of the binary n-bit counter remain unchanged, even if the coding inputs of the η-bit parallel register 5 at this time state change. The next change of the states of the outputs of the parallel parallel register 5 is possible only at the next launch of the device.

So, providing the coding inputs of the η-bit parallel register 5 at the moment the device starts up on the state start input, co corresponding to the binary representation of the generated sequence number, the output of the first adder 7 modulo two in the sequential code will form the required number.

As already noted, in the dynamic mode of the binary n-bit counter 2, when the information input from the output of the first adder 7 | modulo two, the последовательность-sequence arrives, the ground potential at the input of the switching on of the modulator 3 from the output of the OR-NOT 6 element is maintained to ensure the switching on of the modulator 3. Simultaneously with the binary ϋ-sequence formed at the information input of the modulator 3, the sequence A ^ arrives at the control input of the modulator from the output of the first digit of the binary digit counter 2. Since the sequence at the output of the first digit of the binary η-bit counter 2 has the form A ^ = 0101, ... 01, then the odd elements formed on and formational inlet modulator 3 ϋ-sequence corresponds to the zero potential of the control input of the modulator 3, and even elements - a single potential.

In the on state, at the output of the modulator 3, one of the four elements of the generated four-coded signal (sequence of four elements) is output, which we denote as, b,

The logic of the modulator 3 is set as follows:

5 1177910 6

H- ° X

r-4

L, if ϋ.

V

β if ϋ {/ ·

if A = 0

Ί

if ϋ £ => O | if ϋ £ "= · 1

if A ^ = 1,

one

those. when the information input has an odd ϋ-sequence element, which is determined by the state at the control input, then, depending on the value of the ϋ-sequence, the modulator outputs an information output _{: the} L / or IL symbol (D, and oC 15 when the- sequences

equal to "0", and β ^ when "1". If there is a single potential at the control input, which corresponds to an even element of the ϋ-sequence at the information input of the modulator 3, then it outputs an o or Y symbol to output 4, and o, when the-sequence element is "0" and Y · when "1 ".

Thus, a device for generating four-coded sequences provides increased accuracy by improving the correlation properties of the generated sequences.

Claims (2)

A DEVICE FOR FORMING FOUR-CODED SEQUENCES, containing a clock pulse generator, a binary η-bit counter and a modulator whose output is an information output of the device, characterized in that, in order to improve accuracy by improving the correlation properties of the generated sequences ^, η-bit is entered into it parallel register, η adders modulo two (where η = 1,2 ..., η), η elements AND, OR-NOT element and KZ-trigger, to the clock input of which and the input of the binary C-bit counter the clock generator output is connected, This 8-input short-trigger is the device start input, and the K-input of the входΛ-trigger and the first input of the OR-NOT element are connected to the output of the ηth digit of the binary bit counter, to the clock input of which is bit parallel register and the enable switch of the modulator is connected to the output of the element IPI-ΗΕ, κ to the second input the output of the short-circuit trigger is connected, the outputs η of the elements AND are connected to the inputs of the first modulo-two adder, the output of which, as well as the output of the first digit of the binary η-bit counter are connected respectively to the information and control inputs of the modulator, and to the first input of the first element I (where 5 = = 1,2, ... n) and to the first input () +1) of the modulo two adder is connected the output of the) digit of the binary L-bit counter, while the output of the first discharge of the U-bit parallel register is connected to the second input of the first element d, and the outputs of the other bits of the p. -bit parallel register are connected to the second inputs of the corresponding modulo-two adders, whose outputs are connected to the second inputs of the corresponding elements And, the inputs of the η, -bit parallel register are the coding inputs of the device. 5C .... 1177910 one 1177910 2