SU1700770A1 - Code combination separator - Google Patents

Abstract

The invention can be used in discrete communication systems. The purpose of the invention is to simplify the device and improve accuracy. To do this, the device introduced the elements OR - NOT 2 and the divider 3 frequency. The latter generates gating pulses to control the operation of trigger 1 and counter 4, and the element OR NOT 2 detects that there are inconsistencies in the characters commuted to its input by multiplexer 5 received by the code combination and blocks the operation of the device. 1 il.

Description

The invention relates to the field of radio engineering and communications and can be used in digital information transmission systems.

The aim of the invention is to simplify the device and improve accuracy. ;

The drawing shows a structural electrical circuit of a device for extracting a code pattern.

The device contains a trigger 1, the element OR NOT 2, the divider 3 frequency counter 4 and multiplexer 5.

A device for extracting a codeword operates as follows.

In the initial position at the input of the device, there is a logical O trigger 1 and counter 4 are in the zero state, and divisor 3 is in the state corresponding to the beginning of the character of the code combination.

At the output of the element OR NOT 2 there is a signal of logical 1, holding

trigger 1, counter 4, and divider 3 in the initial state.

When a signal arrives at the device input with a logic level of 1 (start signal), the output of the OR-NOT 2 element generates a logical O signal, which allows the divider 3 to work, trigger 1, and counter 4.

At the output of the divider 3, after the arrival of eight pulses of the reference frequency, a gating pulse is formed, which is located in the middle of the starting burst. This front edge writes to the trigger 1 code 1 and translates counter 4 into a position in which multiplexer 5, through the second input, sends a logical 1 signal to the first input of the OR-NOT element 2, which indicates the start of sprinkling. This signal generates at the output of the element OR NOT 2 a signal of logical O, which allows the divisor 3 to work with the counter 4 and the trigger 1. The pulse is stro (I

with

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The output that arrives at the second input of the OR-NOT 2 element during the pulse action generates a logical signal O at its output, thereby eliminating the effect of the transient when switching trigger 1, counter 1 and multiplexer 5.

The second gating pulse appears at the output of the splitter 3 sixteen pulses after the first and is located in the middle of the first code message. If the input signal is a logical 1, i.e. the first bit of the code combination, the second gating pulse writes to the trigger 1 code., and transfers the counter 4 to the next position. Multiplexer 5 sends the signal t to the first input of the element OR NOT 2 to the first input, thereby allowing the divider 3, trigger 1 and counter 4 to work.

The third gating pulse writes the O code into the trigger 1, if the second bit of the code com- bination is at the input, and translates the counter 4 to the next position. At the same time, multiplexer 5 through the fourth information input falls from inverse trigger output 1 code 1 to the first input of the element OR NOT 2, allowing the divider 3, trigger 1 and counter 4 to work. Similarly, the selection and subsequent bits of the code combination are performed.

The signal at the overflow output of counter 4 is a signal that detects the arrival of the desired combination.

If in a code combination, instead of a signal, logical O (logical 1), then at the first input of the element

OR-NOT 2 a logical O signal is sent. At the same time, after the end of the strobe pulse, a logical 1 signal is generated at its output, which resets the divider 3, the trigger 1 and the counter 4 to the zero state. The device enters the standby mode of the beginning of the code combination.

Claims (1)

 Invention Formula A device for extracting a code combination containing a multiplexer trigger and a counter, the bit outputs of which are connected to the control inputs of the multiplexer, characterized in that, in order to simplify the device and improve accuracy, a frequency divider and an element OR NOT, the output of which is connected to the combined the installation inputs of the frequency divider, trigger and counter, whose input is combined with the first input of the OR-NOT element and the recording entry of the trigger and connected to the output of the frequency divider, the second input of the OR-NOT element is connected to The output of the multiplexer, the first input of which is combined with the trigger input, is the device input, the forward trigger output is connected to the multiplexer inputs corresponding to the logical units in the code combination, and the inverse output of the subconnect to the inputs of the multiplexer corresponding to the logical paths combinations, the counter replenishment output being the output of a device whose clock input is the input of a frequency divider.