RU1817241C - Pulse counter - Google Patents

Abstract

Usage: the invention relates to devices of pulsed technology and can be used in digital technology, in automation and microcircuitry. SUMMARY OF THE INVENTION: A pulse counter contains three-bit elements, each of which contains an OR element (19), an AND element (20), three triggers (16-18), which have an extension of inputs D by I. 4 ill.

Description

FIG. 2

The invention relates to pulse technology and can be used in digital technology, in automation, and in microcircuitry.

The purpose of the invention is to increase the speed, simplify the circuit of the counter and improve its characteristics, namely, the implementation of the counter completely in the direct logic system, when direct pulses are fed to its counter input and trigger switching occurs along the edges of these pulses.

Figure 1 shows a diagram of a counter; Fig. 2 is a diagram of a three-bit element; Fig. 3 is a timing diagram of a counter; figure 4 - diagram of the D-trigger.

The pulse counter (Fig. 1) contains 1-3 - three-bit elements; 4 - counting input T of the counter; 5 - reset input R of the counter; 6 - control input of the last three-bit counter element; 7-15 - outputs Q1-Q9 bits of the counter.

Each three-bit element (Fig. 2) contains 16-18 - first 16, second 17 and third 18 triggers: 19 - OR element; 20 - element And; 21 - counting input T; 22 - reset input R; 23 - control input V; 24-26 - outputs of the first 24-Q1, second 25-Q2 and third 26-Q3 bits; 27 - RT transfer port; 28 - PV control output.

The operation of the counter is illustrated by the time chart in Fig. 3, in which the individual pulses are indicated by numbers 29-71.

Initial state - all the triggers in Fig. 2 are in state 0, at the control input 23 there is a signal 1 from the output of PV, the second three-bit element. There is a signal at the output 28 PV. At the other inputs and outputs, there are signals 0.

At the input of T we give pulses.

The first pulse 29 switches the trigger 16 to state 1, the pulse front 30 is formed at its output 24. The pulse 29 passes to the pulse outputs of the QR triggers 17 and 18 - pulses 31 and 32: At the output 28, the pulse 33 is formed. At the outputs. 26-24 Q3-Q1 of the element, code 001 corresponding to the number 1 in the Fibonacci code is generated.

The second pulse 34 switches triggers 16 and 17 - pulses 30 and 35, passes to the pulse outputs QR of the first 16 and third 18 triggers - pulses 36 and 37. At the output 28, the pulse front 38 is formed. At outputs Q3-Q1 - code 010, corresponding to the number 2 in the Fibonacci code.

The third pulse 39 switches the second 17 and third 18 triggers - pulses 35 and 40, and comes to the pulse outputs of the first 16 and second 17 triggers - pulses 41 and

42. At outputs Q3-Q1, code 100 is generated.

corresponding to the number 3 in the Fibonacci code.

Fourth pulse 43 toggles

only the first trigger 16 is pulse 44, and

passes to the pulse output of the second trigger 17-pulse45. At the output of the OCH-QI, a code 101 is generated corresponding to the number 4 in the Fibonacci code,

The fifth pulse 46 switches the first

16 and third 18 triggers to state 0. Now all the triggers of the first three-bit element 1 are in state 0. Pulse 46 passes to the pulse outputs QR of all triggers of the three-bit element 5 - pulses 47-49, and passes through the And 20 element the transfer output 27 is a pulse 50. At the output 28, the front of the pulse 51 is formed. The pulse 50 from the output 27 goes to the input 21 of the second three-bit element and switches the trigger 16 to state 1 in it. At the same time, the output 10 a pulse 52 is generated in the counter, and at the outputs 12-7 of the Q6-Q1 counter, a code 001000 is generated, corresponding to number 5 in the Fibonacci code.

5 At the output 28 of the second element 2 and at the input 23 of the first element 1, a pulse 53 is formed. With a signal 0 at the input 23, the third trigger 18 in the three-bit element cannot be switched

0 input 21 pulses.

The sixth pulse 54 acts the same as the first pulse 29, a pulse 55 is generated at the output 24. At the outputs 12-7 of the counter Q6-Q1, the code 001001 is generated.

5 corresponding to the number 6 in the Fibonacci code. The seventh pulse 56 acts in the same way as the second pulse 34, a pulse 57 is generated at the output 25. At the outputs 12-7 of Q6-Q1, the code 001010 corresponding to

0 to the number 7 in the Fibonacci code.

The eighth pulse 58 switches the second trigger 17 to state 0 - pulse 57, passes to the pulse outputs QR of all triggers - pulses 59-61, and to the output

5 of the And 20 element - pulse 62. The pulse 62 enters the second 2 three-bit element, in which the first 16 and second 17 triggers switch to the 0 and 1 state - pulses 52 and 63. At the input 23 of the first three-bit element 1, a front is formed pulse 1. At outputs Q6-Q1, a code 010000 is generated corresponding to the number 8 in the Fibonacci code.

The next five pulses (65-69) act in the same way as the first five pulses (29. 34, 39, 43, 46). At the output 27 of the first three-bit element, a transfer pulse 70 is formed again, and at the counter outputs 11 and 12, a pulse drop 63 and a pulse front 71 are formed. At the outputs .15-7 Q9-Q1, iodine 000100000 corresponding to the number 13 in the Fibonacci code is generated.

D-flip-flops with an additional pulse output are widely known (see, for example, the book by V.V. Klimov, Pulse keys in digital devices, 1989). Figure 4 shows a diagram of such a trigger. It contains an RS flip-flop 72 and a pulse switch 73 with memory of the control signal. D-trigger also has input D 74, switching (clock) input 75, direct 76 and inverse 77 outputs and pulse output 78, K

Technical advantages of the proposed pulse counter in the Fibonacci code::; ::

simplicity of the circuit, in comparison with the prototype device, there are no elements NOT, fewer AND elements, fewer connections between elements;

improvement of characteristics, namely, the proposed device is triggered by forward pulses and is triggered by the edges of these pulses, while the prototype device is triggered by the decays of these pulses (which is a drawback, since both circuits are executed in the direct logic system and are triggered by forward pulses );

increased performance, which can be seen only in the comparison of devices. It is known that the delay in the formation of a pulse at the output of the trigger relative to the switching pulse for most triggers is TTr 4 Tle, where Tle is the delay in the propagation of the pulse by an OR-NOT or NAND. It is also known that the delay in the propagation of a pulse by the elements U and U1I is equal to Ti Tili - 2 Tle. On the decline of the counting pulse in the prototype device, the triggers and are switched. therefore, the delay in generating a signal at the inputs of AND elements is A T e. Serially connected AND and OR elements introduce a propagation delay of 4 pulses, too. The total delay is 8 Tle. The maximum pulse frequency that can be applied to the counting input of the counter is 1/8 tele. At

of the proposed counter, the propagation delay of the pulse through the pulse switch is 2 Tle and through the And element is also 2 Tle, total 4 Tle. Therefore, mdmaximal5 at a frequency that can be fed to the counting input of the proposed device is equal to 1-4 TLE, i.e. twice as much. Thus, the proposed device in comparison with the prototype has twice

0 greater speed.

FORMULA AND SECTION

; Pulse counter in Fibonacci code,

5 containing separate three-bit elements, each of which has a counting input and a control input, a transfer output and a control output, transfer and control outputs of the first three-bit element are connected respectively to the counting input and the control input, respectively (1 + 1} and (1-1) th three-bit elements, each three-bit element contains AND and OR logic elements and three triggers,

5, the inverse output of the first of which is connected to the control output of the three-bit element, the clock inputs of all the triggers are connected and connected to the counting input of the three-bit element, the output is logical0 then the AND element is connected to the transfer output of the three-bit element, and the first input of the OR logical element is connected to the output of the second trigger, characterized in that, for the sake of simplicity, D-triggers

5 are made with additional pulse outputs QR and with expansion along the input D by AND, the inputs D of the first trigger are connected to the inverse outputs of the first and second triggers, the inputs D of the second trigger

0 are connected to the output of the first trigger and to the inverse output of the third trigger, the inputs D of the third trigger are connected to the inverse output of the first trigger, to the control output of the three-bit element and to

5 to the output of the OR element, the second input of which is connected to the output of the third trigger, and the pulse outputs QR of all triggers of the three-bit element are connected to the inputs of the element I.

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FIG. 4