SU1531215A1 - Pulse counter in maximum fibonacci codes - Google Patents

Abstract

The invention relates to a pulse technique and can be used for multi-digit pulse recalculation in a maximum Fibonacci code with P = 1 values with the possibility of increasing the size. The purpose of the invention is to expand the scope. The counter contains three triggers, an OR element, two AND elements, and a clock bus. To achieve the goal, five AND-NOT elements, two control outputs, a reset input and a transfer output are entered into it. 1 ill., 1 tab.

Description

The invention relates to a pulse technique and can be used for multi-digit pulse recalculation in the maximum Fibonacci code with the possibility of increasing the size.

The purpose of the invention is the expansion of the application.

The drawing shows the functional diagram of the pulse counter in the maximum Fibonacci codes for the case.

The table contains codes describing the operation of the counter.

The U1pulses counter in the maximum Fibonacci codes contains 1K-triggers 1-3, the element OR 4, the elements 5 and 6, the clock bus 7, the elements AND-NOT 8-12, the first control input 13, the second control input 14, the first control output 15, second control output 16, reset input 17, transfer output 18. Tact bus 7 is connected to clock inputs of triggers 1–3 and to the first input of the second element AND 6. The reset inputs of the first 1, second 2 and third 3 triggers are combined and connected to the counter 17 input of the counter, direct output of the first 1 trigger connected to the first control output 15 of the counter, to the first 1 inputs of flip-flops 2 and 3 of the second and third bits and to the first input of the first element 5, the output of which is connected to the second input of the second element 6, to the first input of the first element 11 NOT

8, with the first input of the third element AND-NOT 10 and with the second input of the element OR 4, the inverse output of the first trigger 1 is connected to its 1-input

and the second input of the second element is AND- HE 9, the output of which is connected to the first K-input of the second trigger 2, the direct output of the second trigger 2 is connected to the second 1-input of the third trigger third, -NOT

9, the second input of the first element

And 5 and with the first entry n of that element

:

ate

That AND-NO 12, the output of which is connected to the third K-input of the first trigger 1, the inverse output of the second trigger 2 is connected to the second control output 16 of the counter, to the first input of the fourth element AND-HE 11 and to the first input of the element OR 4, the output of which is connected to the first K-input of trigger 3 of the third bit, the direct output of trigger 3 of the third bit is connected to the second input of the fourth element AND-NOT 11 and to the third input of the first element And 5, the inverse output of trigger 3 of the third bit yes connected to the second input of the fifth element NAND 12 , and the first 13 and second 14 control inputs of the counter are connected respectively to the second and third inputs of the first AND-NE element 8, the output of which is connected to the second K-input of the first trigger 1, to the second input of the third AND-NE element 10 and from the second To - the trigger input 3 of the third bit, and the outputs of the third element AND-NOT 10, the fourth element AND-NOT 11 and the second element And 6 are connected respectively to the second K-input of the second trigger 2, with the third K-input of the third trigger 3 discharge and with the release of 18 carry.

The pulse counter in the maximum Fibonacci P-codes operates as follows.

To increase the size of the overall circuit, the series of counter modules are combined as follows. The transfer output 18 of each module is connected to the counting input 7 of the next module, the control outputs 15 and 16, respectively, with the control inputs 13 and t4 of the previous module, and the reset inputs 17 are combined,

In the initial state of the 1K-flip-flop, the counter modules are in zero states. The inputs 13 and 14 of the first module contain the potentials, respectively, of zero and the logical unit from the control outputs 15 and 16 of the subsequent module. In this case, the trigger 1 of the first module is in the write mode of the unit, and the triggers 2 and 3 are in the write mode zero.

Upon the arrival of the first clock pulse, the counter, containing two modules, is set to 100,000,

five

0

When the second clock pulse arrives, the signal level at the I and K inputs of trigger 1 of the first module corresponds to the zero recording mode, at the I and K inputs of trigger 2 to the switching mode, and on the I and K inputs of trigger 3 to the zero recording mode, therefore the counter set to state 010000.

Before the arrival of the third clock pulse, trigger 1 of the first module is in the write mode of the unit, triggers 2 and 3 are in the storage mode, and the third clock pulse sets the counter to the state of 110,000.

Before the arrival of the fourth clock pulse, trigger 1 of the first module is in the storage mode, trigger 2 in the switching mode, trigger 3 in the unit recording mode, and the fourth clock pulse sets the counter to state 101000.

Before the fifth clock pulse arrives, the trigger 1 of the first module is in write mode zero, trigger 2 is in unit write mode, trigger 3 is in storage mode, and the fifth clock pulse sets the counter to state 011000. Before the sixth clock pulse arrives the trigger 1 of the first module is in the unit write mode, the triggers 2 and 3 are in the storage mode and the clock pulse sets the counter to the state 111000.

Prior to the arrival of the seventh clock pulse, the triggers 1–3 of the first module are respectively in the zero recording mode, the unit recording mode, and the switching mode. At the output of the element And 5 there is a potential of a logical unit that permits the passage of the eighth clock pulse through the element 6 and the output 18 of the transfer to the counting input of the subsequent module. The counter is set to state 010100.

The first control input 13 of the first module is set to the potential of the logical unit coming from the first control output 15 of the second module.

Thus, the first module of the counter before the arrival of the twelfth clock pulse operates in a mode similar to the mode of the module from the second to the sixth cycles of operation.

0

five

0

In this case, the trigger 1 of the first module is in the storage mode, the trigger 2 is in the switching mode, the trigger 3 is in the recording mode of the unit. The twelfth clock pulse passes through the elements of AND 6 and the transfer output 18 of the first module to the count input 7 of the second module and the counter is set to tion 101010.

The control inputs 13 and 14 of the first module are set to the potentials of a logical zero, coming from the control outputs 15 and 16 of the new module.

Thus, the first module in cycles from the thirteenth to the fifteenth operates in a mode similar to the mode of the module in cycles from the fifth to the seventh,

In the cycles from the sixteenth to the twentieth, the work of the first module is similar to the mode of its operation in the cycles from the third to the seventh.

In the cycles from the twenty-first to the twenty-fifth, the work of the first module is similar to the mode of its operation in the cycles from the eighth to the twelfth.

In the cycles from the twenty-sixth to the twenty-eighth, the operation of the first module is similar to the mode of its operation in the cycles from the fifth to the seventh.

In the cycles from the twenty-ninth to the thirty-third, the work of the first module is similar to the mode of its operation in the cycles from the seventh to the twelfth.

In the thirty-third clock cycle, a clock pulse passes through the AND 6 element of the second module and through the transfer output 18 enters the counting input of the subsequent module and the counter is set to the state 101,010.1, etc.

Thus, the mode of operation of the module is determined by the state of the bit triggers of the subsequent module, this allows the modular organization of the counter, which leads to unification.

Claims (1)

Invention Formula The pulse counter in the maximum Fibonacci codes containing the first, second and third triggers, the OR element, the first and second And elements, the clock bus connected to the clock inputs of the triggers and the first 0 five 0 five 0 five 0 S 0 five the input of the second element AND, characterized in that, in order to expand the field of application, it further comprises AND-NOT, the first and second control inputs, the first and second control outputs, the reset input and the transfer rate, first and fifth elements, and the inputs reset the first, second and third flip-flops combined and connected to the reset input of the counter, the first flip-flop trigger output is connected to the first control output of the scaling circuit, with the first 1-inputs of the second and third bit triggers a AND, the output of which is connected to the second input of the second element AND, to the first input of the first element and -NE, to the first input of the third AND-NOT element and to the second input of the OR element, the inverse output of the first discharge trigger is connected to its 1-input the home and the second input of the second NAND element, the output of which is connected to the first K input of the second discharge trigger, the direct output of the second discharge trigger is connected to the second I input of the third discharge trigger, to the first input of the second NO entry , the second input of the first element And with the first input of the p element That NAND, the output of which is connected to the third K input of the first trigger, the inverse output of the second discharge trigger is connected to the second control output of the counter, to the first input of the fourth element NAND and to the first input of the element OR, output which is connected to the first K input of the third bit trigger, the direct output of the third bit trigger is connected to the second input of the fourth NAND element and to the third input of the first And element, the inverse output of the third bit trigger is connected to the second input of the fifth AND element -NO, and the first and second The control inputs of the counter are connected respectively to the second and third inputs of the first NAND element, the output of which is connected to the second K input of the first trigger, to the second input of the third AND device, and to the second K input of the third trigger, and the outputs of the third NAND element, the fourth NAND element, and the second AND element are connected to the second K-input of the second trigger, with the third K-input of the third trigger discharge and transfer output, respectively. f r-ua 2 r