SU921094A1 - Decimal counter - Google Patents

Description

(54) DECIMAL COUNTER

one

The invention relates to a pulse technique, in particular to pulse counters.

A decimal counter is known that contains four counting flip-flops, a match element and a driver, and the inverse outputs of the first and fourth triggers are connected to the inputs of the match element, the output of which is connected to the unit inputs of the second and third triggers 1.

The disadvantage of this counter is its low noise immunity, since the probability of interference (for example, through the power supply circuits) is high, which can cause a false trigger of the counter.

Also known is a decimal counter containing an input bus, four flip-flops, a delay element and an I, direct output element (ed of each flip-flop, except the last one, is connected to the counting input of a subsequent trigger, the output of the And element is connected to the installation inputs to the second and third triggers, the input bus is connected through a delay element with a counting input of the first trigger, the direct output of which is connected to the first input of the element And, the second and third inputs of which are connected by co2

responsibly with the input bus and with the direct output of the fourth trigger 2.

The disadvantages of the known device are low noise immunity, expressed in false positives of counter triggers in the event of impulsive noise or interference, as a result of which in three higher bits one of the forbidden states can occur, in addition, the use of the outputs of the main memory element (trigger first time yes)

10 for building a feedback loop causes the device to become functionally unreliable, which limits the scope of application of the device.

The aim of the invention is to improve noise immunity.

15

To achieve this goal, a decimal counter containing an input bus, four flip-flops and an And element, the direct output of each flip-flop, except the last one, is connected to the counting input of the subsequent

20 triggers, the output of the element I is connected to the inputs of the installation in the unit of the second and third triggers, two additional triggers are introduced, the element is NOT and the inertial element, the input and output of which are connected respectively to the direct output of the fourth trigger and to the input of the installation of the first additional trigger unit, the installation input to zero of which is connected to the input bus, with the clock input of the first trigger and through the element NOT with the clock input of the second additional trigger, the inverse output of which is connected to the first input ale enta And, the second input of which is connected to the direct output of the first additional trigger.

FIG. 1 shows a functional diagram of a decimal counter; in fig. 2 - time diagram of the ten-meter operation.

The counter contains triggers 1-4, element 5 NOT, trigger 6, element 7 I, trigger 8, inertial link-9 and input bus 10.

The input bus 10 is connected to the counting input of the trigger 1, to the input of the zero setting of the trigger 8 and connected via element 5 NOT to the counting input of the trigger b, the inverse output of which is connected to the first input of the element 7, the second input of which is connected to the forward output of the trigger 8 , the installation input in the unit of which is connected to the output of the inertial link 9, the input of which is connected to the direct output of trigger 4, the direct outputs of flip-flops 1, 2 and 3 are connected respectively to the counting inputs of flip-flops 2-4, the output of element 7 I is connected to the inputs installation in one Itza Triggers 2 and 3.

Inertial link 9 contains a capacitor 11 and resistors 12 and 13, the first end of the last of which is connected to the input of the inertial link 9, the output of which is connected to the second end of the resistor 13, to the first end of the register 12 and to the first plate of the capacitor And, the second plate of which is connected to the second end of the resistor 12 and with a common bus 14.

FIG. 2 shows timing diagrams of 15-23 signals, respectively, on the input bus 10, the output of element 5 NOT, the inverse output of trigger 6, the direct outputs of trigger 1. and 8 the output of element 7 I.

The counter works as follows.

When applying to the reset bar (not shown in Fig. 1) the signal of setting the counter to the initial position, the binary number 0000 is set in the counter, and simultaneously to the initial state is set to the trigger 6.

After applying the counting pulses to the input busbar 10 (Fig. 2, 15), the trigger 1 switches and the binary number 0001 will be fixed in the counter (Fig. 2, 18-21). At the same time, the counting pulses arrive at the counting input of the trigger 6 through the element 5 NOT (Fig. 2, 16) and the Inverted output of the trigger 6 removes the signal (Fig. 2, 17), in addition, the counting pulses also arrive at the input of the zero setting of the trigger 8 and the first counting pulse trigger 8 is set to the zero state. The counting process continues in a similar way until the number 0111 is fixed on the counter (Fig. 2. 18-21). After the arrival of the eighth counting pulse, a code combination 1000 (Figs. 2, 18-21) is set at the same time, after switching the trigger 4, through the inertial link 9, the signal, affecting the trigger -8, switches it from zero to one state, which before the arrival of the ninth counting pulse (Fig. 2, 22). The signals taken from the output of the trigger 6 and the trigger 8, are fed to the inputs of the element 7

And, from the output of which a signal is removed (Figs. 2, 23), which, acting on the installation inputs of the flip-flops 2 and 3, switches them from the zero to one state and the code combination 1111 is set at the outputs of the flip-flops 1-4 (Fig. 2 ,

° 18-21).

The tenth count pulse sets the counter to the initial state 0000, starting from the eleventh pulse, the counting process is repeated.

J As a result of interference (for example, power supply) or in the three higher bits, one of the forbidden states may occur, however, due to the fact that c. the feedback circuit is installed trigger 8 and the inertial element 9, the penetration of interference at the input of the unit in the unit trigger 8 is excluded. This is due to the fact that the appearance of interference at the installation of the zero trigger of the trigger 8 does not affect the operability of the latter, since the control of the trigger 8 at the setup input to zero is produced by the first counting pulse, which by setting the trigger 8 to the zero state , does not respond to subsequent counting pulses.

In the case of interference on the installation input of the unit in the interval between the first and eighth pulses, the trigger 8 also does not switch, since the inertial link is set to the unit input of the trigger 8, the constant of which is chosen for a longer duration of the interference. Thus, during the duration of the impulse noise, the signal at the input of the unit to the trigger unit 8 tie has time to change to the level of its operation, consequently, the false influence of the interference on the trigger 8 and, thereby, the effect of the interference on one of the inputs of element 7 is eliminated.

Claims (2)

At the other input of element 7, the penetration of interference in the interval between the first and the eighth counting pulses is forbidden by element 5 and the trigger 6. Thus, in the three higher bits, one of the false states, which could occur in the event of interference, t . spurious switches are prevented. Moreover, the exclusion of feedback from the output of the first digit of the decimal counter also facilitates the operation of the device, since the harmful effect of the load on the previous stage is eliminated. Claims A decimal counter containing an input bar, four flip-flops and an element, direct output of each flip-flop, except the last one, is connected to the counting input of a subsequent flip-flop, the output of the And element is connected to the inputs of the unit of the second and third flip-flops, characterized in that , in order to improve noise immunity, two additional triggers are introduced into it, the element is NOT and the inertial element. 9 dess 4 input and output of which are connected respectively with the direct output of the fourth trigger and with the installation input into the unit of the first additional trigger, the installation input with which zero is connected to the input bus, with the clock input of the first trigger and with the second input with the clock input |) a, the inverse output of which is connected to the first input of the element I, the second input of which is connected to the direct output of the first additional trigger. Sources of information taken into account in the examination 1. V. V. Matveev and others. Instruments for measuring ionizing radiation. M., Atom-izdat, 1972, p. 546, fig. 229 (c). 2. USSR author's certificate number 409386, cl. H 03 K 23/00, 1972 (prototype). and and and and and and If t pg J 1123. eight ten 7