SU409385A1 - - Google Patents

Description

MULTI-DECADE RECORDING DEVICE

one

The invention relates to the field of automation, telemechanics and is intended for pulse counting devices.

Recalculators are known in which the high and low bits of all decades are associated with a decoder, the output of which is connected to a circuit for writing code in the decades. One; in such schemes, with a total delay of the signal more than for the period of the input pulses, the multi-decade counting device does not work correctly. In this connection, the operating frequency of the counting device is reduced. In addition, such a counting device requires the use of decades of the same speed, because otherwise it is necessary to extend the code rewriting signal for the second and subsequent, their decades.

The purpose of the invention is the elimination of errors when rewriting the code) at the cut-off frequencies and improving the reliability of the non-counting device.

The invention consists in creating devices in which the time interval for recording and the duration of the code write pulses are expanded by skipping L counting pulses (L 2, 3 ...), which ensures: 1 ss the first operation of the device at the boundary frequencies. To accomplish this, an auxiliary counter, counting the number of missed pulses, as well as an additional trigger and coincidence circuits that control the operation of the multi-decade counting device, are introduced into the mimic decade counting device. The number of missed counting pulses L, taken into account by the choice of decipher: a multi-decade counting device, should provide a time interval L-gmiv (where G is the minimum period of counting pulses) exceeding the delay in the code recording circuit / c. ensure that the alias code entry /:m.-, i.e.

L 7 min: i.i n.:i. .

A further increase in L is impractical.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - timing diagrams, but with 1 operation of the device.

The multi-decade iReal device contains the circuits 7 and 2 matches, the additional trigger 3, the decade divide. 4, a decoder 5, an all-encompassing counter 6, a zero-signaling circuit 7, a write-pulse decryption circuit 8, a code writing circuit 9.

The device works as follows.

The input signal (Fig. 2, a) is fed to the coincidence circuit 1 (2). Suppose that the input of the circuit BTopoii / is supplied to the logical unit from the output of the additional trigger 3

(Fig. 2, e}, and on. the second input of circuit 2 feeds a logical zero from the output of additional trigger 3. In this case, the input pulses through the circuit / pass (fig. 2, b) to decadal dividers 4. At the moment filling decadal dividers at the output of the decoder 5 1V31N1i. pulse (Fig. 2, d), which transfers the additional trigger 3 to another stable state (Fig. 2, e). Consequently, a logical unit appears at the second input of the circuit 2, and the input pulses are passed to the auxiliary counter 6 (Fig. 2, c). The pulse at the output of the pulse decoding circuit 7 Zero occurs when the first input pulse is received by the auxiliary counter 6 (Fig. 2, g). This pulse resets decadal dividers 4 to zero. The pulse at the output of the write pulse decoding circuit 8 occurs when the third input pulse arrives at the auxiliary counter 6 2, h). This impulse goes to the circuit 9 of the code entry.

Subject invention

A multi-decade counting device containing a write circuit, decade divide 5 bodies, the outputs of the high and low bits of the digits of which are associated with the inputs of the decoder, and a trigger, characterized in that, in order to improve reliability, two two-input matching schemes are entered into it , the first inputs of which are connected to the input signal bus, and the second inputs are connected to the trigger outputs, the output of one matching circuit is connected to the input of decadal dividers, and the output of the other matching circuit is connected to

15 by the input of an additionally inserted counter, the outputs of the cells of the bits of which are connected to the inputs of the decryption circuit of the reset pulses, the output of which is connected to the input of the zero decadalers setting, and to the inputs

20 of the write pulse decoding circuit, the output of which is connected to the input of the code writing circuit, and the output of the high-order counter cell is connected to one of the trigger inputs, the other input of which is connected to the output of the 2 .S encoder.