SU993460A1 - Scaling device - Google Patents

Description

The invention relates to a pulse technique and can be used in instrument making and devices in a discrete processing of information.

A pulse frequency multiplier is known that contains a reference frequency generator, the output of which is connected through a frequency divider to one input of the first pulse counter, another input to which is connected to the input of the frequency multiplier pulse, and a second pulse counter whose input is connected to the output of the logic element OR, whose inputs connected to the input and output of the multiplier of the pulse frequency; inputs of the shift registers are connected to the outputs of the bits of the first pulse counter; the outputs are connected to the corresponding inputs of the comparator unit, s inputs connected to the outputs of the bits of the second pulse counter, shift register clock inputs are connected to the input of the multiplier 13, the pulse frequency,

A disadvantage of the known device is limited functional features:.

The closest in technical essence to the invention is a pulse frequency multiplier comprising a one-shot, three pulse counters, a register, three AND elements, an OR element, a comparison element, the first inputs of which are bitwise connected to the outputs of the register, the second inputs to the outputs of the first counter pulses, and the output with the first input of the first element

10 OR, the reference frequency generator, the output of which is connected to the counting input of the first pulse counter, the counting input of the second pulse counter is connected to the output of the first

15 elements And, the trigger and the input pulse shaper, the output of which is connected to the input of the C2 one-shot.

The disadvantage of the known device is the limited functional capabilities, as a result of the impossibility of its use for dividing the frequency of the input pulse sequence.

The purpose of the invention is the expansion

25 functionality by combining the functions of multiplying and dividing the pulse frequency in one device.

To this end, in a scaling device. Containing one-time er,,

three pulse counters, a register, three AND elements, an OR element, a comparison element, the first inputs of which are bitwise connected to the register outputs, the second inputs to the outputs of the first pulse counter, and the output to the first input of the first OR element, and the reference frequency generator, the output of which is connected to the counting input of the first pulse counter, and the counting input of the second pulse counter is connected to the output of the first And element, an additional comparison element, a decoder, additional AND OR, inverters and a fourth counter are introduced to pulses, the zero input of which is connected to the output of the one-shot, the counting input from the output of the first additional element AND, and the output to the input of the decoder, the first output of which is connected to the first inputs of the first, first additional and second additional elements OR, the second output from the first to the second and third additional elements are And, and the third output is to the first input of the second element And and the first inputs of the fourth and fifth additional elements And and the input of the first inverter, the output of which is connected to the first input of the first additional element I, the second input of which is connected to the input bus, while the second inputs of the second and fifth additional elements I are connected to the control bus directly, and the second inputs of the third and fourth additional elements I through the second inverter, the outputs of the second and third Additional elements And are connected to the first inputs of the third and fourth additional OR elements, the second inputs of which are connected to the outputs of the fourth and fifth additional elements AND, the output tert its additional element OR is connected to the first input of the third element AND and the first input of the sixth additional element AND, the second input of which is connected to the output of the second element AND, the second input of which is connected to the output of the additional comparison element, and to the first input of the seventh additional element AND, the second the input of which is connected to the first input of the first element AND and the output of the fourth additional element OR, and the output to the second input of the first additional element OR, the output of which is connected to an embosser the input of the second pulse counter, the bit outputs of which are connected to the first inputs of the additional comparison element, the second inputs of which are connected to the discharge outputs of the third pulse counter

the zeroing input of which is connected to the output of the second additional element OR, the second input of which is connected to the output of the sixth additional element AND, and the counting input to the output of the third element AND whose second input is connected to the output of the reference element and the output of the reference frequency generator to the second the entrance of the first element I.

The drawing shows a block diagram of the device.

The device contains a one-shot 1, counters 2-5 pulses, register 6, decoder 7, elements AND 8-17, elements OR 18-22, elements 23 and 24 of comparison, generator 25 of the reference frequency, inverters 26 and 27, control bus 28, input bus 29, the output bus 30.

The device works as follows.

At the initial time, the one-shot 1 produces a single pulse, which sets the counters -5 to the zero state. Register b is recorded in any known way by dividing the coefficient equal to the specified coefficient K of multiplication. Bus 28 is provided with a high level control signal.

0 When the first pulse of the multiplied sequence of periodic pulses arrives on the bus 29, the counter 5 switches to the next state. At the same time, a pulse appears at the second output of the decoder 7, opening element 12.

The divider of the reference frequency, which includes counter 2, register b, the element OR 18 and the element 23 of the comparison, divides the frequency of the generator 25 In accordance with a given division factor recorded in the register,

Signals from the output of the element 23 with frequency

 TO

where ROP pulse frequency generator -25,

pass through the element 8 to the counting input of the counter 3 and fill it with the arrival on the bus 29 of the second pulse of the multiplied frequency.

With the arrival of the second input pulse, the counter 5 switches to the next state. At the same time, a pulse appears at the third output of the decoder 7, causing the element 8 to close, disconnecting the counting input of the counter 3 from the output of the element 23. At the same time, opens through the element 15 and the element 22, element 10, connecting the counting input of the counter 4 to the output , generator 25 ..

High level signal from the third output of the decoder 7 through the inverter

26 closes element 11, as a result of which the counting input of counter 5 is disconnected from bus 29. At the same time, element 9 opens, connecting the output of element 24 to the output bus of the device.

The second input pulse of the multiplied frequency determines the length of the period following the input pulse sequence.

During the first period of the multiplied frequency, fi pulses from the output of element 23 are recorded in counter 3, i.e. reference frequency divider output

where Fon is the pulse repetition frequency of the reference frequency generator;

FBK - frequency of the input pulse sequence}

K is the division factor of the reference frequency, equal to the specified multiplication factor.

Counter 4 counts the pulses arriving at its counting input from generator output 25 to comparison comparison codes of counters 3 and 4, current counter code 4 being compared with fixed counter code 3. When comparing counter codes 3 and 4, the output of element 24 produces a pulse that enters through openings element 9 on the device galley bus and zeroing input of counter 4, resetting it to the zero state. Counter 4 begins again to fill with pulses from generator output 25 until the next comparison of counter codes 3 and 4, and so on. The frequency of operation of the element 24, which determines the magnitude of the multiplied frequency, is equal to

.L-k Fe "

Frequency multiplication will continue until set to zero. Counter 5 (for example, by restarting the one-shot 1) After setting the counter to zero, the signal from the first output of the decoder 7 sets the counters 2-4 to zero. After that, the device is ready for the next launch. The device operation was described above when the frequency was multiplied.

 When frequency is divided into bus 28, a low level control signal is applied.

With the arrival on the bus 29 of the first pulse of the dividend sequence of periodic pulses, the counter 5 switches to the next state. In this way, the pulse from the second output of the decoder 7 opens through (element 13 and element 22 element 8), as a result of which the pulses from the generator 2.5 output go to the counting input of counter 4 and fill it before the second pulse of the dividend frequency arrives on bus 29.

With the arrival of the second input pulse, the counter 5 switches to the next state. In this case, the pulse

from the third output of the decoder 7 closes the element 8, disconnecting the counting counter 4 from the output of the generator 25. Simultaneously with this, through the element 14 and the element 21 the element

8, so that the pulses pass to the counting input of the counter 3 from the output of the element 23. - Signal. high level from the third output of the decoder 7 through the inverter 26 closes

11, whereby the counting input of the counter 5 is disconnected from the input bus 29. At the same time, the element 9 connects the output of the element 24 to the output bus of the device.

During the first period divisible

Frequencies in counter 4 are recorded.

Front pulses From the output of the generator 25.

on

h2

-,

Rwh

Counter 3 counts the pulses arriving at its counting input from the output of element 23, i.e. the output of the divider frequency reference until the comparison of the codes of Counters 3 and 4. The current

5, the counter code 3 is compared with the fixed counter code 4. When comparing the counter codes 3 and 4, the output of element 24 produces a pulse, which is fed through element 9 to the output bus of the device and the zeroing input of counter 3 (through open element 16 and element 20 by resetting it to the zero state). Counter 3 starts to fill up again.

5 pulses from the output of the reference frequency divider, i.e. output element 23 to the following comparison of the codes of counters 3 and 4, etc. The frequency of operation of the element 24, which determines the magnitude of the divided frequency, is equal to

- on ...

on K-FBX ex

The frequency division will continue from until the zero state of the counter 5 is set, as a result of which the signal from the first output of the de-raffle 7 will set the counters 2-4 to the zero state. After that, the device is ready for the next launch.

The introduction into the well-known multiplier of “iacTOTu” pulses of the counter of new elements and the relations between them, ensuring the interaction of all the functional units of the device, allows-. It is necessary to extend the functionality of the frequency pulse cf) i by combining the functions of multiplying and dividing the frequency in one device.

Claims (1)

1. Author's certificate. USSR 580634, cl, H 03 K 5/156, 1976. 2, USSR Author's Certificate 425315, cl. H 03 K 7/00, 1972.