SU930641A1 - Pulse length discriminator - Google Patents

Description

one

The invention relates to a pulse technique and can be used to select pulses by duration in a predetermined range from a sequence of pulses with different durations.

A pulse selector is known in terms of duration, comprising a clock pulse generator, an AND element, a pulse counter, two decoders, a pulse shaper, a delay device, and an inverter l.

The disadvantage of this selector is that it requires the use of additional devices to perform the pulse separation function, since it only provides information that the pulse width of the input signal is equal to the specified one.

In addition, this selector has a limited scope, since the discreteness of measuring the input signal impulse duration is equal to the follow-up period of the clock generator pulses, and the tolerance range of the input signal’s impulse duration from the preset is also equal to the clock pulse output time factor, which leads to unstable operation of the device, since the phase shift of the front frotn of the pulses of the input signal relative to the pulses of the clock generator is random.

ten

A pulse selector is also known in terms of duration, which contains a clock pulse generator, the output of which is connected to the subtractive inputs of N counters connected in series, an iso logical element whose inputs are soy ({ina with the outputs of the counter, a coincidence element whose inputs are connected to the outputs of loan K + 1 counters, trigger and second match element jj2j.

20

Claims (2)

The disadvantage of such a selector is low reliability due to the complexity of the circuit and low noise immunity. The purpose of the invention is to improve noise immunity and reliability. The supplied circuit is achieved by the fact that in a pulse selector, in duration, comprising a clock pulse generator, the output of which is connected to the subtractive inputs of three counters, the first two of which are connected in series, a logic element, one of the inputs of which is connected to the output of the second counter, the input of which is connected to the loan outputs of the second and third counter, a pulse shaper is inputted, the output of which is connected to another input of the logic element, the output of which is connected to the recording input the third counter, and the input of the pulse driver is connected to the input terminal and the input-record of the first counter, and the loan output of each counter is connected to its blocking input. FIG. 1 shows the structural scheme of the proposed selector; in fig. 2 - time diagrams for his work. The pulse selector contains the clock pulse generator 1, the first counter 2, the pulse generator 3, the second counter 4, the logical element AND-NOT 5, the third counter) 6, the coincidence element 7, the selector input 8, the selector output 9, the group of inputs 10 2, a group of inputs 11 of the counter 4, a group of inputs 12 of the counter 6. The pulse selector operates in the following manner. The clock pulse generator 1 generates rectangular pulses with a period TQ (Fig. 2a), which are fed to the subtractive inputs of counters 2, 4 and 6. In the absence of input signal pulses at input 8, counters 2, 4 to 6 are in the zero state, Since in the case of a non-zero state of any 1 counter, the signal of a logical unit at its loan output enters the lock input of this counter and permits the passage of pulses from generator 1 to the subtracting input of this counter until, at the output of the loan counter on vits signal l cal zero, which corresponds to its zero state of the output and prevents blocking of the passage of pulses from the generator 1 to the subtracting input of the counter. Thus, in the initial state, i.e. npvi no input pulses, at the outputs of saelvia counters. 2, 4 and 6 there is a logical zero signal, therefore the output of element 7 coincidence sets the signal of the logical unit, since the signal of logical zero at the output of element 7 coincidence will be at a signal of logical zero at the output of the counter 4 and the signal of the logical unit at the output of the counter 6 The input signal pulses (Fig. 2b) are fed to input 8, which is the recording input of counter 2, with the leading edge of the input signal, i.e. front 1/0, counter 2 records the code of the number m, / Tjy determining the minimum required pulse width of the input signal, and input of the driver 3, while the driver 3 outputs a pulse corresponding to the falling edge of the input signal pulse (Fig. 2a). Since state 2 is different from zero, then at its loan output there is a signal of a logical unit that arrives at its blocking input and allows the passage of pulses from generator 1 to the subtracting input of this counter. After PC time relative to the leading edge of the input signal pulse at the loan output of this counter, a logical zero signal is received, which enters the blocking input of this counter and prohibits the passage of pulses from generator 1 to the subtracting input of this counter, and also enters the recording input of counter 4 and the front I / O records in it a code of a number defining the zone of permissible deviations of the duration 1 max m1n of the pulses of the input signal where t is the maximum required duration of the pulses of the input signal; LjYij - minimum required pulse width of the input signal. Since the state of counter 4 is different from zero, a logical unit signal appears at its output of the loan, which permits the passage of pulses from generator 1 to the subtracting input of this counter and, through time (m P) T relative to the leading edge of impulse 1 A signal of a logical knock appears at the output of the loan of this counter, which is fed to the blocking input of this counter and prohibits the passage of pulses from generator 1 through its subtractive input. Thus, at the output of counter 2, pulses appear (FIG. 2B), whose duration is numerically equal to T, the leading edge of which coincides with the leading edge of the input signal, and at the output of counter 4, pulses appear (Fig. 22), whose leading edge is shifted by time T relative to the leading edge of the input signal pulse, and the duration is numerically equal to П TQ. Therefore, if the pulse corresponding to the back pulse of the input signal (Fig. 2nd), issued by shaper 3, comes before the time tn Tg or after the time (HI + I) TQ, it means that the pulse duration of the input signal is either less than or is greater than the specified value, then the output of the logical element AND-NOT 5 has no impulse, since the impulse from the output of the borrowing of counter 4 (Fig. 22) and the impulse from the output of the former 3 (Fig. 2a) do not coincide in time, which means that the state of the counter 6 unchanged, i.e. it remains in the zero state, and, accordingly, the exit state of the element 7 coincidence does not change either. If the pulse corresponding to the trailing edge of the input signal pulse (Fig. 2o.), Issued by shaper 3, comes in the time interval from m T to (t + P) TO, then this indicates that the pulse width of the input signal is equal to the specified one, and a pulse appears at the output of the AND-NE 5 element (Fig. 2e), since the pulse from the output of the counter 4 is borrowed (Fig. 22), arriving at the first input of the AND-HE 5 logic element, and the pulse from the output of the driver 3 ( Fig. 2a) coincide in time. The front 1/0 of this pulse, corresponding to the rear ontu of the pulse of the input signal, in counter 6 records the code of the number m + P, corresponding to the maximum permissible pulse duration of the input signal. Since the state {1 of counter 6 is different from zero, the logical unit at its loan output pushes into the lock input of this meter and allows the passage of pulses from generator 1 to the subtracting input of this counter (Fig. 2 (c)). The output of the counter 6, which prohibits the passage of pulses from the generator 1 to the subtracting input of this counter, is at a time (m - f) TQ relative to the falling edge of the input signal. Consequently, a pulse is outputted at output 9 of the coincidence element (FIG. . 2), shifted by time ( P + W) Td relative to the leading edge of the input signal pulse, with a duration equal to the input signal pulse duration, since the inverting input of the coincidence element 7 receives a signal from the output of the counter 4 borrowing (Fig. 22), and the direct input of the coincidence element 7 The signal from the output of the counter 6 is delivered (4ng. 2 g), the coincidence element 7 gives a pulse equal to the duration of the input pulse, since a logical zero signal arrived at its inverting input, and a logical one signal was sent to the direct input. It is possible to change the duration of a selectable pulse and the tolerance zone by changing the code by groups of inputs 1O-12 | however, the accuracy of the selector in the entire tuning range is maintained. The use of additional devices for performing pulse selection functions is not required. The formula of the invention is a Pulse Selector in duration, containing a clock pulse generator, the output of which is connected to the subtractive inputs of three counters, the first two of which are connected in series, a logic element, one of the inputs of which is connected to the output of the second counter, the coincidence element, the inputs of which connected to the borrowings of the second and third counters, characterized in that, with a circuit for improving noise immunity and reliability, a pulse shaper is inserted into it, the output of which is connected to another input l cal element whose output is connected to the input of the third counter recording and the input pulse shaper is connected to the input terminal and the input of the recording of the first counter, wherein each borrow output of the counter is connected with its inlet lock. Sources of information taken into account during the examination 1. USSR author's certificate number 577663, cl. H 03 K 5/20, 22,11,77. 2. USSR author's certificate Xt 790241, cl. НОЗ К 5 / 2О, 12.12.78 (protottsh). cS -9-tih rill “S t tip. l EL I1 T ly " 71-1 Vb 23 ... m ... n f23..m ... ny25 .-- m ... " well ) To