SU1004956A1 - Time interval train to digital code converter - Google Patents

Description

The code contains six coincidence elements, a clock pulse generator, the output of which is connected to the first inputs of the first and second element matches, the second inputs of which are combined and connected to the forward output of the enable trigger, and the outputs are connected to the counting inputs of the first and second counters, respectively pulse driver, three deceleration elements, a memory device and a control trigger, the direct output of which is connected to the third input of the first and the first input of the third match element, the last input its one is connected directly to the first control input of the storage device and through the first delay element to the set zero input of the second counter, the inverted control trigger output is connected to the third input of the second and the first input of the fourth match element, the output of the last of which is connected directly to the second input of the recording control of the storage device and through the second delay element to the input of the zero setting of the first counter, outputs, the fifth and the same elements of the match respectively with the R - and S - inputs of the trigger of inclusions, and their first entrances with Start and Stop buses, respectively, the output of the third delay element connected to the second inputs of the third and fourth elements of the match, and the outputs of the bits of the first and second counters are connected to the first and the second group of information inputs of the storage device, respectively, are introduced R5 - a trigger, an AND-NO element and a Kipp-relay, the output of which is co-connected with the second inputs of the fifth and sixth matching elements, the input of the third delay element, the counting input control trigger and R-input R5 of the trigger, S is the input of which is connected to the output of the pulse former, and the direct output is connected to the first input of the NAND element, the second input of which is connected to the output of the clock generator, and the output p & le. The drawing shows a block diagram of the Converter sequence of time intervals in a digital code. The converter contains a generator of 1 clock cmp gls, elements 2 and 3 of match, element 4, counters 5 and 6, gearbox relay 7, memory of device 8, control trigger 9, start trigger 1U, match elements 11 and 12, RS trigger 13 , delay element 14, pulse shaper 15, coincidence elements 16 and 17, delay elements 1.8 and 19. The device works as follows. The clock pulse generator 1 operates in the self-oscillation mode, forming square-wave pulses of a given tracking frequency. In the initial state (before the start of counting), zero output potentials of the 1O flip-flop and 7% relay relays 7 are set, and at the outputs of the counters 5 and 6, code values equal to zero. To do this, before the measurements are started, an external signal is set to the state O of the counters 5 and C) and the enable trigger 1O (the setting circuit in O is not shown). The measurement starts when the input signal element 11 starts. The first one, which came after that, the input pulse generated by the shaper 15 into a rectangular pulse of a given duration and amplitude sets the trigger 13 to the input element 4 potential. The first clock pulse, which arrives at the second input of element 4, generates a logical O signal at its output. At the time when the clock pulse ends at the output of element 4, the IS potential does not reestablish the unit potential, which is used to start the control relay 7, which generates a control pulse trigger 9.: This pulse changes the state of the trigger. 9- controls (for example, I is set to the direct output), and, also, trigger 13, on the forward output of which O is set, locking the 4 AND-NO element, moreover, having passed through the coincidence element 11, the control impulse changes $ The trigger 10, at the direct output of which is set I. Thus, the resolving potentials are fed to the two inputs of the element 2 coincidence, and the potential to be resolved to the input of the element 3 coincidences from the trigger 9. Therefore, starting from this point in time, the clock pulses from generator 1 through element 2 coincidences are postpiled to the input of counter 5 and are counted by it.

The second input pulse from the output of the imaging unit 15 changes the state of the trigger 13, opening element 4 AND-NOT. A clock pulse 7 is triggered by a clock pulse. The control pulse, which enters the input of the trigger 9, changes its state to the opposite one (O, and at the inverse output, I), thereby applying the resolving potentials to elements 3 and 17 of the coincidence and forbidding ones to elements 2 and 16 of the coincidence.

Same | a control pulse delayed by delay element 14, sufficient time for the transition process to terminate in control trigger 9, passes through a matching element 17 and rewrites the contents of counter 5 into a storage device 8 and is additionally delayed by delay element 19 for a time sufficient for rewriting the contents of the slider 5 into the memory 8, sets the counter 5 to O. The same control pulse sets the trigger 13 to its initial state.

The third input pulse using trigger 13, element 4 AND-NOT and cr-relay 7 detects the status of control trigger 9, which starts counting the clock pulses of counter 5, as well as recording the contents of counter 6 into the storage device 8 followed by zeroing the counter 6.

When the next pulse arrives at the device input at any time, a pulse of control is generated at the output of the switch-relay 7 along the trailing edge of the first clock pulse received from the output of generator 1. Thereby, the change in the state of the trigger 9 is organized at times that do not coincide with time occurrences of a clock pulse, which eliminates the possibility of loss of a clock pulse or writing it to both counters at the same time. The clock pulses are counted alternately by counters 5 and 6.

Since Kfk control trigger 9 is in each state for a period of time equal to the interval between input pulses, the digit codes read from counters 5 and 6 into memory 8 are proportional to the time intervals between input pulses, and the dependence of the measurement accuracy on the the number of intervals when conducting one series of measurements.

The copying of information into the recording device 8 from one counter is performed during the operation of another counter.

The conversion of time slots to a digital code ends when element 12 sig- is received at the input. Stop, after which the next input impulse generates a control impulse at the output of the output and release 7. This impulse passes through the coincidence element 12 and sets the trigger Yu to be included in O, thereby closing elements 2 and 3 of the coincidence.

Thus, in the proposed device, the measurement of the sequence of time intervals between pulses in real time is performed, the uncertainty in the registration of clock pulses is eliminated, which leads to an increase in the accuracy of measurements of the duration of the sequence of time intervals.

Claims (1)

1. USSR author's certificate number 336793, cl. N OZ K 13/02, 1968