SU1654980A1 - Number-to-time converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in radiometric equipment and synchronization devices, measurement technology. The purpose of the invention is to improve the accuracy and expansion of the range of clock frequencies. The converter contains a pulse generator, four triggers, a pulse counter, an input code bus, a start bus, an output bus, a logic unit bus, and zero. The goal is achieved by organizing the counting, recording and transfer of a pulse counter, which allows to obtain a time interval, the front and the fall of which are delayed relative to the front of the reference frequency pulses by the trigger switching delay value. 2 Il.

Description

The invention relates to automation and computing and can be used in radiometric equipment, synchronization devices and measurement technology.

The purpose of the invention is to improve the accuracy and expansion of the range of clock frequencies.

FIG. 1 shows a functional diagram of the converter; in fig. 2 - time diagrams of his work.

Converter code - time interval contains a generator of 1 pulses, triggers 2-5, pulse counter 6, input code bus 7, start bus 8, output bus 9, logical unit bus 10 and logical zero bus 11.

The Converter operates as follows.

When power is applied to the device, the 2-5 trigger at several intervals of the input reference frequency is set to the zero state (the triggers are switched by a negative differential reference

frequencies) and are in this state before the arrival of the trigger pulse via bus 8.

The start pulse enters the bus 8 from the output of the high-speed frequency divider and has a delay relative to the reference clock frequency of the generator 1 pulses, equal to the delay of one logic element, not exceeding the duration of the pulse frequency reference, and the duration equal to half the period of the frequency of the generator 1 when the output signal type generator meander. The start pulse sets trigger 2 to state "1" and confirms state "About trigger 3. Setting trigger 2 to state" O occurs on the first negative reference frequency difference after the end of the trigger pulse. Thus, a positive pulse appears at the forward output of flip-flop 2. The delay of the negative differential pulse relative to the negative differential of the reference frequency is equal to the switching time of this trigger. This impulse

about ate

J

CO 00

enters the / -input of the trigger 3, / (- the trigger input is in the logical state "O and, since the negative differential pulse is delayed relative to the negative differential of the reference frequency, the trigger 3 switches to the logical logic" 1 by the first negative differential after the end of the pulse trigger input to the / -input of this trigger. The signal from the direct output of trigger 3 is fed to the transfer enable and counting inputs of counter 6, allowing the calculation of negative frequency reference drops. As the counting enable input counter and 6 can use / - and / (- inputs of the first trigger of the counting line of meter triggers, and the transfer resolution input (inverter outputs of the counting trigger and the reference frequency of the generator can be used as the transfer resolution input).

When counting pulses, trigger 3 remains in a logical "1" state, since the / - and / (- trigger inputs receive levels of a logical "0 and with the arrival of each negative differential frequency reference the state of a logical" 1 "is confirmed.

At the moment of filling the counter b, the overflow signal appears at the transfer output of the counter, the duration of which is equal to the pulse width of the input reference frequency. For reliable operation of the device, it is necessary that the overflow signal from the transfer output of counter 6 has a delay relative to the positive differential of the reference frequency of generator 1 is not more than half the period of the reference frequency (with a square wave signal).

The impulse from the transfer output of the counter 6 is fed to the inputs of the installation in the "1 S-flip-flops 3 and 4. The flip-flop 4 is set by this impulse to the state of logical" 1, at / (- the input of the trigger 3 appears logical The negative differential of the reference frequency after the occurrence of the transfer pulse trigger 3 does not change its state, as it is held in the state of a logical "1 transfer pulse for counter 6 applied to the priority S input of the installation. The second negative reference differential after the appearance of the transfer pulse counter 6 trigger 5 is set to the logical "1" state, since at its input the logical level "1 continues to remain, and at the / (- input - logical level" O from the outputs of the trigger 4. By this negative differential of the reference frequency, trigger 3 is set to logical "O, since its / -input is set to a logical level" O, at / (- the input continues to remain the logical level "1 from the direct output of trigger 4, which by the time of this negative reference frequency difference remains in the state" 1 because zade rzhki switch it.

The trigger 4 by the second negative differential of the reference frequency after the occurrence of the transfer pulse of the counter 6 is set to the logical state "O, and the next negative differential sets the trigger 5 to the logical state" 0.

The pulse from the direct output of the trigger 3 is used to resolve the counting and transfer: on the counter 6, after its completion the trigger 5 generates a pulse with a duration equal to the repetition period of the frequency to write the input code to the counter 6. After that, the device goes into the standby mode of the next trigger pulse bus 8.

Thus, at the forward output of trigger 3, a positive impulse of duration

tstrob l- (2 + N) + & t, h

0 where N is the controllable binary code from the bus

management;

f ™ -talk frequency pulse generator;

A / - conversion error. The pulse front delay (iW0i) with respect to the negative reference frequency difference is the switching time of the trigger 3 from the logical "O to logical" state 1. The delay of the pulse (& ady) relative to the negative reference frequency difference is the switching time of trigger 3 from the logical state "1 to the logical state" O.

The error in the formation of the time interval of the proposed converter is

A // ass 01 / ass y.

A delayed pulse from the transfer output of counter 6 can be used as an output signal.

The converter is operable at the maximum pulse generator frequency at which the conversion error is less than the repetition period:

/ Hymax - ---,

Ti - | - / | hell

5 where ba is the maximum switching delay time of either the first trigger of counter 6 or one of the triggers 2-5;

ti is the minimum pulse duration, which is necessary for reliable operation of the triggers (usually

TI bad);

/ gimax - maximum frequency of the pulse generator.

0

0

Claims (1)

Invention Formula The converter code is a time interval containing a pulse generator, a pulse counter whose information inputs are the corresponding input code buses, and the first trigger, whose S input is a trigger bus, characterized in that, in order to improve the accuracy and range clock frequencies, the second, third and fourth triggers are entered into it, the C inputs of which are combined with the C input of the first trigger and the counting input of the pulse counter and connected to the output of the pulse generator, / - and / (- inputs The / -input of the second flip-flop, the / -input of which is the trigger bus, and the S input is combined with the S input of the third flip-flop and connected to the pulse output of the pulse counter, the inputs of which enable and carry enable are connected and connected to the direct output of the second trigger, / (- the input of which is combined with the / input of the fourth trigger and connected to the direct output of the third trigger, the first and third triggers, respectively; the inverse output of which is connected to / C-in- merged and is, respectively, the width of the fourth trigger, the direct output by the ends of the logical zero and the logical unit, which is connected to the installation input; pulses. The / -input of the second flip-flop, the / -input of which is the trigger bus, and the S input is combined with the S input of the third flip-flop and connected to the pulse output of the pulse counter, the inputs of which enable and carry enable are connected and connected to the direct output of the second trigger, / (- the input of which is combined with the / input of the fourth trigger and connected to the direct output of the third trigger, the inverse output of which is connected with the / C input of the fourth trigger, the direct output of which is connected to the input of the pulse counter installation. 1 Reel 2