SU1721813A1 - Pulse driver - Google Patents

Abstract

The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals. The purpose of the invention is to increase functional reliability. The device contains a generator of 1 clock pulses, input bus 7, two triggers 8 and 9, two counters 12 and 13 pulses. Introduction to the device of five elements AND-NOT 2-6 and two triggers 10 and 11 allows to eliminate the failure of the device when a single pulse arrives on the input bus, which increases the reliability of its operation. 2 or

Description

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The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals.

The purpose of the invention is to increase the functional reliability due to the absence of malfunction when a single pulse arrives on the input bus.

Figure 1 shows an electrical functional diagram of the device; 2 shows timing diagrams for his work.

A device for generating pulses contains a clock pulse generator 1, AND-NE elements 2-6, an input bus 7, triggers 8-11, counters 12 and 13 pulses, information buses 14 and an output bus 15. The output of the clock pulse generator 1 is connected to the first inputs elements AND-NOT 2 - 5, the second input of the element AND-NO 2 is connected to the second input of the element AND-NOT 3, the direct output of the trigger 9 and the D-input of the trigger 10, the output - to the write input of the counter 12 pulses, the first C-input trigger 10 and the first R input of the trigger 11, and the third input with the inverse output of the trigger 10 and the second input element AND-NOT 5, the output of which is connected to the subtractive input of the counter 12 pulses, with a summing input of the counter 13 pulses and the first C-input of the trigger 9, and the third input with the inverse output of the trigger 9 and the second input of the element IS-HE 4, output which is connected to the write input of the pulse counter 13, the second C-input of the trigger 10 and the second R-input of the trigger 11, and the third input to the direct output of the trigger 10 and the third input of the AND-HE element 3, the output of which is connected to the second C-input trigger 9, with a subtracting input of the counter 13 pulses and a summing input m counter 12 pulses. The R input of the latter is connected to the R input of the pulse counter 13 and the direct output of the trigger 11, the information inputs with the corresponding information inputs of the pulse counter 13 and the corresponding information buses 14, and the output with the first C input of the trigger 11. The second C input the latter is connected to the output of the pulse counter 13, the inverse output of which is connected to the output bus 15 and the first input of the element AND-HE 6, and the D-input with the output of the element AND-HE 6, the second input of which is connected to the input bus 7 and the C-input trigger 8, inverse output of which nen same with its D-input and straight exit - a D-input of flip-flop 9.

The device works as follows.

In the initial state, before the arrival of a series of pulses on the input bus 7, a low voltage level (level O) is in effect. Triggers 8-10 are in zero

states, i.e. at their direct outputs are levels of the Log. O, and the trigger 11 is in a single state; a high voltage level acts on its direct output. Level Log.1 from the output of the trigger 11 enters the

0 reset inputs R reversible counters 12 and 13, keeping them in their original zero state.

The elements AND NOT 2-4 are in the closed state and do not pass the clock pulses of the oscillator 1 to the corresponding inputs of the circuit elements. The closed state of the NAND elements 2-4 (level 1 at the outputs) is maintained by arriving at the inputs of the elements of the O levels from the direct outputs of the flip-flops 9 and 10. The NAND element 6 is also in the closed state due to Level Log. t) from the input bus 7.

5 The AND-NE element 5 is in the open state, since both inputs of this element receive levels 1 from the inverse outputs of the flip-flops 9 and 10. The clock pulses of the generator 1, inverted by the AND-E element 5, are simultaneously fed to the subtracting input reversible counter 12 and to the summing input of the reversible counter 13, as well as to the input C1 of the synchronization trigger 9.

5 Due to the fact that the inputs R of both counters 12 and 13 have a level 1, which prohibits the counting of clock pulses from the output of the AND-HE element 5, negative transfer pulses, arriving at synchronous but counting pulses, appear only at the output of counter 12 which is set to subtraction mode. At the same time, the pulses at the output of the negative transfer of the counter 13 do not appear, since it is set in the addition mode.

On an n-bit bus 14, a code of a certain number N is permanently applied, which is previously written to that counter 12 or 13, which will work on addition, as an additive that exceeds the zero value (in this case, (FIG. 2) N 2). Due to this, when the corresponding counter goes into the subtraction mode of the number of clock pulses that it has accumulated during the period of addition, the possibility of premature transfer pulses at its output in the event of the next pulse of the series is excluded. At the same time, due to the number N, the accuracy of converting a series of pulses into a rectangular pulse At is set, where Tti is the period of the following clock pulses. Those. the accuracy of the conversion is determined by the length of time, At, which is counted from the moment of the expected occurrence of a pulse, a series. During the time At, the counter 12 or 13 additionally subtracts the number of pulses N 2, and when the third clock pulse arrives at its trailing edge, the output signal ends.

On the output bus 15 in the initial state the level O acts.

Figure 2 shows two cases of the arrival of a series of pulses, respectively, with the parameters Ti, Ti ;. T2, T2 (Ti is the period of the pulse of the first series, n is the pulse duration of the first series, T2 is the period of the pulse of the second series, Ta is the duration of the pulse of the second series).

In the first case, when the first pulse of a series enters the input bus 7 along the leading edge of this pulse, the trigger 8 switches to one state. Level 1 from its output goes to the D input of the trigger 9, which also switches to a single state on the falling edge of the clock pulse from the output of the element AND-NOT 5. This creates conditions for the passage of the pulses of the generator 1 through the element AND-NOT 2. The element NAND 5 is closed, and NAND elements 3 and 4 are kept in the closed state.

On the leading edge of the next pulse coming from the output of the element AND-NOT 2, the trigger 11 switches to the zero state, and on the output bus 15 the output signal starts to form in the form of level 1. At the same time, the element AND-NOT 6 opens and at its output sets level O. At the same time, blocking is removed from the inputs R of counters 12 and 13. At counter 12, the code of the number N arriving through the bus 14 is recorded at its installation input V of level O. The counter of the outputs 13 remains the same as the zero code combination, as on his mouth ovochnom V input acts at this time the level 1 output from AND-NO element 4.

On the falling edge of the pulse from the output of the element AND-NOT 2, the trigger 10 is switched to one state. In this case, the element AND-NOT 2 is closed, and the elements AND- NO 4 and 5 continue to be held in the closed state. Conditions are created for the passage of the pulses of the generator 1 through the NAND element 3. The counter 12 moves from the subtraction mode to the addition mode, and the counter 13 goes from the addition mode to the subtraction mode. When the pulses appear at the output of the NAND 3 element, the counters go into a continuous clock counting mode. At the same time, the first impulse from the output of the NAND 3 element, passing to the negative transfer output of the counter 13, does not cause the reverse switching of the trigger 11 to the one state, since the D-input of the trigger 11 receives the level O from the output of the IS-NOT 6 element .

At the moment of termination of the transfer pulse, a single code combination is established at the output of the counter 13. After some time, the first impulse of the series on the bus 7 ends, after which the AND-HE element 6 closes and a level 1 is set at its output. The trigger 8 continues to remain in one state without changing the meter operation modes.

The contents of counter 12 begin to increase relative to the number N previously recorded in the counter, and the contents of counter 13 decrease relative to the unit code pattern that occurred at its output.

When a second pulse arrives on bus 7 on the leading edge of this pulse, the trigger 8 switches to the zero state, after which the falling edge of the pulse from the output of the AND-NOT element 3 switches to the zero state of the trigger 9. At the same time, the AND-HE element 3 closes , and the elements AND-NOT 2 and 5 are held in a closed state. Conditions are created for the passage of the pulses of the generator 1 through the NOT-4 element. The operation of the counters is suspended. Upon the appearance of a pulse at the output of the NAND 4 element, the number 13 is recorded in the counter 13, regardless of its state, via the bus 14. The state of the counter 12 does not change, i.e. the number accumulated in it corresponds to the period following the Ti pulses of the series.

On the falling edge of the pulse from the output of the element AND-NOT 4 to the zero state, the trigger 10 is switched, the element AND-NOT 4 is closed. The elements AND-NOT 2 and 3 are still held in the closed state. Conditions are created for the passage of the pulses of the generator 1 through the element IS-NOT 5. Therefore, the counter 12 is switched back from the addition mode to the subtraction mode, and the counter 13, respectively, from the subtraction mode to the addition mode.

When the pulses from the output of the element AND-NE 5 are received, the contents of the counter 12 begin to decrease from a certain number corresponding to the period Ti of the series of pulses, and the contents of the counter 13 increase relative to the number N recorded in the counter 13. This continues until the next third impulse of the series, on the leading edge of which the trigger 8 again switches to one state. At the same time, the negative transfer impulse will not have time to form at the output of the counter 12 operating on the subtraction, since its content will not be reduced to zero due to the number N previously recorded in the counter 12 before the addition mode.

Then all the processes are repeated. The operation of the counters is temporarily suspended. Then in the counter 12 the number N is recorded again, and in the counter 13 the number accumulated by it in the addition mode, corresponding to the period of the PT pulses of the series, is stored. After that, the counter 12 goes to the add mode, and the counter 13 goes to the subtraction mode. The contents of counter 12 begin to increase with respect to the number N, and the contents of the counter 13 decrease with respect to the number accumulated over the period Ti.

If the next impulse of the series does not appear, then after a time interval Dx (Fig. 2) relative to the moment of its expected occurrence, counter 12 will take away the additional number of impulses N 2 coming from the output of the AND-NE 5 element and will generate when the third impulse appears the first negative transfer (overflow) pulse, on the falling edge of which trigger 11 switches to the initial one state. Thus, on the output bus 15, the output signal is terminated.

In the second case (Fig. 2), when a train of pulses arrives at the input bus 7, but already with different parameters r and T2, all the processes are repeated in a similar way. The difference is that the last counter, which works on the subtraction at the moment of formation of the transfer pulse, will be the counter 13, and not the counter 12, as in the first case.

It should also be noted that the device does not need to be reset after power is turned on, since the scheme of the device is characterized by a symmetrical design. For example, if, after turning on the power, the triggers 8-10 are randomly set to a single initial state, and not to the zero state mentioned earlier, then only the initial operating modes of the counters change. The first impulse of the series will switch the trigger 8 to the zero state, and the counter 13 will work first on the addition, not the counter 12. On the subtraction in

In this case, the first will start the operation of the counter 12.

The output signal on bus 15 will be generated in a similar manner.

In the device, the conversion error over the entire range is constant and is determined by the value

.

Claims (1)

Invention Formula A device for generating pulses, containing an input bus connected to the C input of the first trigger, a clock pulse generator, a second trigger and two pulse counters, characterized in that, in order to increase functional reliability due to the absence of a single input bus impulse, five NAND elements and two triggers are entered into it, the first input of the first NAND element is connected to the output of the clock generator and the first inputs of the second, third and fourth AND elements, the second the input is with the second input of the second NAND element, the direct output of the second trigger and the D-input of the third trigger, the output with the recording input of the first pulse counter, the first C input of the third trigger and the first R input of the fourth trigger, and the third input - with the inverse output of the third trigger and the second input of the fourth NAND element, the output of which is connected to the subtractive input of the first pulse counter, with the summing input of the second pulse counter and the first C-vhrdom second trigger, and the third input - with the inverse output of the second trigger and the second m input of the third element IS-NOT, the output of which is connected to the recording input of the second pulse counter, the second C-input of the third trigger and the second R-input of the fourth trigger, and the third input - with the direct output of the third trigger and the third input The output of which is connected to the second C-input of the second trigger, subtracting the input of the second pulse counter and the summing input of the first pulse counter, the R-input of which is connected to the R-input of the second pulse counter and the direct output of the fourth trigger, D-inputs - with the corresponding the D-inputs of the second pulse counter and the corresponding information buses, and the output with the first C-input of the fourth trigger, the second C-input of which is connected to the output of the second pulse counter, the inverse output with the output bus and the first input of the first AND-N element and D-input-output of the fifth element AND-NOT, the second input of which is connected to the input bus. -w -and M I 10 and C2 S2