SU1160550A1 - Single pulse shaper - Google Patents

Abstract

A SINGLE PULSE FORMER containing three series-connected flip-flops and an element AND whose output is connected to the R-input of the third flip-flop, the output of which is connected to the R-inputs of the first and second flip-flops, while the clock signal bus is connected to the C-inputs of the second and third triggers characterized in that, in order to increase stability and speed, the input bus is connected to the C input of the first flip-flop. The D-input of which is connected to its R-input, and the inverse output is connected to one of the inputs of the And element, the other input of which is connected to the inverse output of the second trigger.

Description

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The invention relates to a pulse technique and can be used in devices for converting, processing and transmitting information.

A device for forming a single pulse is known, which contains an element AND and three flip-flops 1.

The disadvantages of this device are the low stability of the output pulse duration, since it generates shorter duration pulses in those cases when the control signal ends at the moment of formation of the output pulse, as well as low response time due to the need for two synchronization pulses to generate one output pulse and set shaper reset.

The closest to the invention to the technical essence is a single pulse shaper, containing three successively connected flip-flops and element I.

The output element And is connected to the R-input of the third trigger, the output of which is connected to the R-inputs of the first and second flip-flops, and the C-inputs of the second and third flip-flops are connected to the synchronization pulse bus 2.

A disadvantage of the known device is its low stability, caused by the appearance of a continuous sequence of output pulses after the action of a control pulse, if the response time of the first trigger is longer than the response time of the second and. the third trigger and the element I. In this case, after the arrival of the control pulse and the third trigger is triggered, the second trigger will be reset and through element I the third trigger will be reset, and the first trigger will remain in one state.

In addition, to generate a single output pulse and set the shaper to the initial state, three synchronization pulses are necessary, which negatively affects the speed of the shaper as a whole.

The aim of the invention is to increase the stability and speed of a single pulse shaper.

This goal is achieved by the fact that in a single pulse shaper containing three series-connected flip-flops and an element, whose output is connected to the R-input of the third flip-flop, the output of which is connected to the R-inputs of the first and second flip-flops, while the sync pulse bus is connected to C -inputs of the second and third triggers, the input bus is connected to the C-input of the first trigger, the D-input of which is connected to its R-input,

and the inverse output is connected to one of the inputs of the And element, the other input of which is connected to the inverse output of the second trigger.

FIG. 1 shows a functional diagram of the device; in fig. 2 and 3 are the timing diagrams of its operation at different temporal locations of the input control pulses and synchronization pulses.

The shaper of single pulses contains the first trigger 1, the input bus 2, the second trigger 3, the third trigger 4, the AND element 5, the bar 6 of the synchronization pulses and the output bus 7.

The trigger input 1 is connected to the input bus 2, and the D and {- inputs with the R input of the trigger 3 and the output of the trigger 4. The direct and Q inverse outputs of the trigger 1 are connected to the D input of the trigger 3 and to one of the inputs of the AND element 5, respectively. The other input element And 5 is connected to the K-input of the trigger 4 and with the inverse output of the trigger 3,

the direct output of which is connected to the J-BXO5 of the trigger trigger 4. Inputs C of the triggers 3 and 4 are connected to the bus 6 of synchronization pulses.

The device works as follows.

After turning on the power and subsequent supply of synchronization pulses, the device, regardless of the initial state of all triggers, assumes the initial state, in which all triggers are in the zero state.

 When the duration of the control signal is longer than the repetition period of the synchronization pulses (Fig. 2), on the leading edge of the control signal received via bus 2 (Fig. 2, a), trigger I switches to one state (Fig. 26),

0 and the nearest synchronization pulse (Fig. 2d) that arrives after this, with its leading edge, sets trigger state 3 to its one state (Fig. 2c). The back front of the same synchronization pulse

 sets trigger 4 to one state (Fig. 2e), and a logical zero taken from the inverse output of this trigger zeroes triggers 1 and 3. Logical units taken from the inverse outputs of these triggers form logical unit (5 Fig. 2e), which flushes trigger 4. After the triggera 4 is set to zero, the blocking potential is removed from the R inputs of the triggers 1 and 3, and the device assumes the initial state. When the next control pulse is applied, the formation cycle repeats, i.e., after the control pulse arrives to form the output pulse and set the device to its initial state

only one synchronization pulse is needed.

Similarly, the device operates in the case when the control signal is a pulse whose duration is shorter than the repetition period of the synchronization pulses (Fig. 3 shows several possible arrangements of the control pulses relative to the synchronization pulses for this case). Thus, the proposed device, regardless of the duration and temporal arrangement of the control pulses, generates a pulse of constant duration at the output. In addition, the performance of the proposed shaper in comparison with the known increases by two times.

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Claims (1)

A SINGLE PULSE SHAPER containing three serially connected triggers and an And element, the output of which is connected to the R-input of the third trigger, the output of which is connected to the R-inputs of the first and second triggers, while the synchronization pulse bus is connected to the C-inputs of the second and third flip-flops, characterized in that, in order to increase stability and speed, the input bus is connected to the C-input of the first trigger. The D-input of which is connected to its R-input, and the inverse output is connected to one of the inputs of the element And, the other input of which is connected to the inverse output of the second trigger. Figure 1 SU „..1160550 I