SU1721824A1 - Variable-ratio frequency divider - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of meters with a variable counting module. The purpose of the invention is to expand the functionality by providing a change in the division ratio. The divider contains a clock trigger 1, input bus 2, nRS-flip-flops 3.1-H.p, output bus 7, AND element 8, initial bus 9, bus 13 of the division factor code. Each RS trigger 3 consists of an OR element and an element I. Separate unblocking of even and odd RS triggers 3 ensures that the distribution of a single potential along the circuit of RS triggers 3 corresponds to the number of pulses on the 2.1 pp bus. f-ly, 4 ill. 3 Ј

Description

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The invention relates to automation and computer technology and can be used in the construction of meters with a randomly varying multi-purpose counting module.

A pulsed frequency divider with automatically changing division factor is known, containing an appropriately connected frequency divider, input and output buses, three AND elements, three triggers, reversing and subtracting pulse counters, a maximum code decoder, a zero code decoder, a delay element constant Memory device.

The disadvantage of this device is complexity.

A controlled pulse frequency divider is known, comprising a pulse counter, a code comparison unit, a control unit, three AND elements, an OR element, an input and an output bus, respectively, which are connected in this way.

A disadvantage of this device is complexity.

The closest in technical essence to the proposed divider is a ring counter-frequency divider containing a clock T-flip-flop and n RS-flip-flops, with the divider input connected to the T-tna trigger input, direct and inverse outputs of each i-ro ( , n) RS-trigger connected respectively to the S- and R-inputs (i + 1) modn-ro RS-flip-flop, the initial setup input is connected to the asynchronous R-inputs of the clock trigger, RS-flip-flops from the first to (n-2) th and asynchronous inputs (n-1) -th and n-th RS-flip-flops, direct output of the clocking trigger It is connected to the synchronization inputs of RS-triggers with odd numbers, and the inverse output is connected to the synchronization inputs of RS-triggers with even numbers.

A disadvantage of the known divider is the limited functionality associated with the inability to dynamically change the conversion factor.

The aim of the invention is to enhance the functionality by providing a change in the division ratio.

In the frequency divider with a variable division factor, containing a clock trigger, the T-input of which is connected to the input bus, n RS-flip-flops, the first R-inputs of the first (n-2) -s of which are connected to the R-input of the clock-trigger, each output The previous RS flip-flop is connected to the second R-input of the subsequent RS flip-flop, the initial setup bus and the output bus, an I element is inserted that controls the RS flip-flop and the dividing ratio code bus, the bits of which are connected to the first

S-inputs of the corresponding RS-flip-flops, the output of the last of which is connected to the S-input of the controlling RS-flip-flop, the R-input of which is connected to the T-input of the clock trigger, direct output - from the output

0 by bus, inverse output with the first input of the element I, the second input of which is connected to the bus of the initial installation, the output with the R-inputs of the (n-1) -th and n-th RS-flip-flops and with the R-input of the clock trigger, etc. my and

5 inverse outputs of which are connected to the second S-inputs of odd and even RS-flip-flops, respectively, each of the RS-flip-flops contains the element OR and

0 AND element, the output of which is connected to the output of the RS flip-flop and the first input of the OR element, the second and third inputs of which are connected respectively to the first and second S-inputs of the RS flip-flop, output - to the first input of the And element, the second and third

the inputs of which are connected respectively

with the first and second R inputs of the RS flip-flop.

Figure 1 shows the functional

a frequency divider circuit with a variable division factor; FIG. 2 is the RS-flip-flop circuit; 3 and 4 are the time diagrams of the operation of the divider with a division factor of 5 and 3, respectively. The frequency divider with a variable division ratio contains a clock trigger 1, the T-clock of which is connected to the input bus 2, n RS flip-flops 3.1-Z.p, output 4 of each previous one of which is connected to the second R-input 5 of the subsequent RS0 trigger 3, and output 4 of the last RS flip-flop Z.p is connected to the S-input of the controlling RS-flip-flop b, the direct output of which is the output bus 7 of the divider, and the inverse - the input of the And 8 element, the other

Input 5 is connected to the initial installation bus 9, and the output is connected to the first R inputs 10 of all RS triggers 3 and the R input of a clock trigger 1, the forward and inverse outputs of which are connected to

0 second 11 S-inputs of odd and even-numbered RS-flip-flops, respectively, the first inputs 12 of which are connected to the corresponding bits of the bus 13 of the dividing ratio code, the input bus 2 of which is connected to the R input

5 control RS-flip-flop 1.

Each of the RS flip-flops 3 (FIG. 2) contains an OR 14 element and an AND 15 element, the output of which is connected to the output of the RS-flip-flop 4 and the first input of the OR element 14, the second and third inputs of which are connected respectively to the first 13 and second 11 s-inputs

RS-flip-flop 3, output - with the first input element And 15, the second and third inputs of which are connected respectively to the first 10 and second 5 R-inputs RS-flip-flop Z.

The divider works as follows.

At the inputs 13.1–13, the n-bit code of the frequency division coefficient q is applied, and to provide a division factor equal to q (), the potential of the inputs 13.1-13.q is zero, and the remaining nq inputs 13.q + 1 - 13.p - single potential. In the course of operation, the potentials at the inputs 13.1-1 З.п can be changed - the division ratio is dynamically changed accordingly.

Let zero potential be applied to all inputs 13.1 - 13.p. Before applying a series of input pulses to the input 2 of the device, issuing a zero signal to input 9, zero potentials are set at the outputs of all RS flip-flops, and the clocking trigger 1 is also set to zero.

With the arrival of the first pulse at the input 2, the trigger 1 remains in the zero state — the state of the flip-flops 3 does not change. On the trailing edge of the first input pulse, the trigger 1 is set to one state — the potential from the direct output of the trigger 1 is triggered 3.1 the specified state trigger 3.1 saves regardless of the state of clock trigger 1, further propagation of a single signal from output 4 of trigger 3.1 to trigger input 3.2 is blocked by zero potentials at the S inputs 11 and 12 tons iggera 3.2. A single signal arrives at S-input 11 of trigger 3.2 only with the arrival of the falling edge of the second pulse at input 2 (when trigger 1 is set to zero) —correspondingly, at the specified time, the potential of a single level appears at the output of trigger 3.2. Similarly, the potential at the output of the 1st RS flip-flop 3.1 appears with the arrival of the falling edge of the 1st pulse at the input 2. Accordingly, a single potential at the output of the flip-flop Z.p appears at the falling edge of the nth pulse at the input 2 At this moment, a single potential is applied to the S-input of the trigger 6 from the output 4 of the RS-flip-flop Z.p, and to the R-input - zero (from the input 2).

Correspondingly, the trigger 6 is set to one, thereby forming a single signal at the output 7 of the divider and a zero signal at its inverse output, which causes the appearance of a zero potential at the output of the AND 8 element, which sets the clock trigger 1 to zero by this in

unit state for odd q and zero for even q), and sets all RS triggers 3.1-Z.p to zero. The state of the trigger 6 does not change, since its S- and R-inputs have zero potentials that preserve the previous (single) state of the trigger 6 until the leading edge of the next pulse arrives at input 2 - the trigger 6 is set to zero. At this point, the divider is restored to its original state, and the cycle of operation of the device described hereinafter is repeated.

When q n, single signals are fed to the inputs 13.n-q of the last RS flip-flops 3.q + 1 - Zp. In this case, the indicated triggers 3.q + 1 - Z.p with the pulse from input 9 are set to the zero state and remain in this state until a single potential appears at the output 4 of the q-ro RS-flip-flop 3.q. With the occurrence of the latter, regardless of the state of the clocking trigger 1, all the 3.q + 1-Z.p triggers are set to one, ensuring that the trigger 6 is set to one and outputting the signal to the output 7 of the divider after the q input pulses 2

Claims (2)

1. A variable division frequency divider containing a clock trigger, the T input of which is connected to the input bus, n RS flip-flops, the first R inputs of the first (n-2) ones connected to the R input of a clock trigger, output Each previous RS flip-flop is connected to a second R-input of a subsequent RS flip-flop, an initial installation bus and an output bus, characterized in that, in order to extend the functionality by providing a change in the division factor, an AND triggering RS trigger is introduced into it. and bus code ratio dividing unit, the bits of which are connected to the first S-inputs of the respective RS-flip-flops, the last of which is connected to the S-input of the controlling RS-flip-flop, the R-input of which is connected to the T-input of the clock trigger, direct output from output bus, inverse output - with the first input of the element I, the second input of which is connected to the bus of the initial installation, output - with the R-inputs of the (n-1) -th and n-th RS-flip-flops and with the R-input of the clock trigger, etc. my and inverse outputs of which are connected to the second S-inputs, respectively, of odd and even RS-tr ggerov. 2. A divider according to claim 1, characterized in that each of the RS-flip-flops contains an OR element and an AND element whose output is connected to the RS-flip-flop output and to the first input of the OR element, the second and third inputs of which are connected respectively to the first and the second S-inputs of the RS trigger, the output to the first input of the element I, the second and third inputs of which are connected respectively to the first and second R inputs of the RS flip-flop. U2 about u A A A A A A A A u9 about vu about & 2 ABOUT % about uu about ъ about ъ