SU1531214A1 - Functional counter - Google Patents

Abstract

The invention relates to a pulse and computing technique and can be used as a multiprogram counting device, a controllable code combination generator, and a multi-mode pulse distributor. The purpose of the invention is to enhance the functionality and scope by providing an additional third recalculation mode. The functional counter contains N bits, each of which has a JK trigger, an installation and synchronization bus, a first bus for controlling the recalculation mode, two AND elements, and in each bit, except the first, an OR element. The third and fourth elements AND, the OR element, the second and the third buses of the control of the recalculation mode are additionally entered into the counter. 2 Il.

Description

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The invention relates to a pulse and computing technique and can be used as a multiprogram counting device, a controlled code generator and a multi-mode pulse distributor.

The aim of the invention is to enhance the functionality and scope by providing an additional third recalculation mode.

Figure 1 shows the N-bit circuit of the functional counter; 2 - Table 1 - 3 formed three different code combinations for the case.

The functional counter contains (FIG. 1) N bits, each of which is made on a 1K-flip-flop 1.1 1 .N, the synchronization input and input of the zero setting of which are connected respectively to the clock bus 2 and the tire 3 of the zero setting, the first And 4 element, the first the input of which is connected to the direct output of the 1K-trigger of the second bit 1.2, the second input - with the K-inputs of the 1K-flip-flops of the first 1.1, second 1.2 and N-ro 1.N bits, and the output - with the K-inputs of IK - triggers from the third to the N- and bits 1.3 - 1.N, the second element And 5, the first) input of which is connected to the direct output of the 1K-trigger of the second p Adding 1.2, and the second input - with the first bus 6 controlling the conversion mode, in each bit, except the first one, contains the element OR 7.1 - 7. (N-1), the output of each of which is connected to the 1-input of the 1K-trigger of its raz da

the first and second inputs of the OR element of each bit 1.1, except the last one, are connected to the first k outputs of the flip-flops, respectively, of the previous one (i-1) and the next one (i + 1), the first input of the element OR 7 ./(N-1) N-ro bit is connected to the direct output of a DC-flip-flop (Nl) -ro bit l. (Nl), the third element And 8, the first input of which is connected to the second bus 9 of the conversion mode control, and the second input - with the inverse output of the K-flip-flop of the N-ro bit 1.N, the fourth element of AND 10, the first input I of which is connected to the inverse of the “first output - I house of the 1K-flip-flop of the first bit 1.1, the second the input is with the third bus 11 controlling the conversion mode, and the output is with the second input of the element OR N-ro bit 7. (N-1), the Nth element OR 7.N, whose inputs are connected to the outputs of the second 5 and third 8 elements And, and the output - with I-Input IK-trigger of the first bit 1.1.

The function counter operates sparingly.

Before creating each of the three possible modes of generating code combinations via bus 3, all the triggers 1.1-1, N are set to zero out of the original states, and the corresponding buses zero, 0, or 1 (1) logical levels are applied to the buses B, 9, and 11. signals according to table 1 - 3 in figure 2.

In the first conversion mode (Table 1), when zero busses are applied to buses 6 and 9, and a single signal is applied to bus 11, the AND 5 and 8 logic elements are locked by the inputs and the zero output signal of the element OR 7 .N maintains a 1K trigger 1.1 in a constant zero logical state. During the clock flow to the bus 2, the clock pulses 1K-triggers 1 are alternately (in reverse order, starting with the last N-ro bit) set to single logical states. In the last N-OM clock cycle, all meter triggers are set to zero starting points. This completes the first reverse cycle of forming linearly increasing code combinations.

Subsequent cycles of forming these codes are similar to the first cycle described.

0

five

.. -

five

0 5 0 5

The repetition period of these code combinations is determined by the extrusion .t, where t is the duration of one recalculate cycle. The second mode (Table 2) of recalculation is created when the zero signal is replaced by a single on bus 6 (with the same signals on buses 9 and 11). By this very element, And 5 is introduced into the overall process of functioning. Due to this, after successively setting IK-flip-flops 1.N - 1.2 (in reverse order, starting from the last bit) into single logical states, in the N-OM cycle of arrival on the bus 2 of a clock pulse under the action of a single output signal of the And element 5, the trigger 1.1 of the first bit is set to one state, and all other triggers are set to zero state. In subsequent recalculation cycles, alternate filling with units 1.2–1.1N of the triggers occurs (in direct order). In the last 2N-OM cycle, all IK triggers are set to zero initial states. This completes the first cycle of forming code combinations of the second counter operation mode.

Subsequent cycles are similar to the first cycle described.

As can be seen from Table 2, the repetition period of code combinations in the second mode of operation of the counter is determined by the suppression. Among these combinations, it is easy to establish a self-complement code 51111. The remaining code combinations (with different values of N) have similar configurations, but differ from each other in length (in terms of code combinations).

To create an additionally introduced third recalculation mode (Table 3), a single signal is applied to bus 9, a zero signal to bus 11, and either a zero or a single signal to bus 6 (the signal on the bus 6 in Table 3 is shown as sign X). At the same time, the element AND 8 opens at the entrance and the element AND 10 is locked (and the state of the element 5 can be arbitrary). As a result, at the second input of the element OR I. (N-I), a constant zero signal is maintained. In the initial state, when all the trigger

The gers are in zero logic states, a single signal from the inverse output of the last bit's trigger 1.N through AND 8 and OR 7, N is transmitted to the 1-input of the IK-trigger of the first bit 1.1. Due to this, after the first clocking impulse IK is applied to the bus 2, the first-stage trigger is set to a single logical state. Subsequent clocking pulses in turn set all the 1.2 - 1.N triggers (in direct order) to one states. In the last (N + 1) -OM cycle of operation, all triggers are again set to zero initial states. This completes the first cycle of forming a straightforward order of forming linearly increasing code combinations.

Subsequent cycles of forming these codes are similar to the first cycle described.

The repetition period of these code combinations is defined by the expression T (N + l) .t.

Claims (1)

Thus, the functional counter allows to provide three different modes of forming code combinations, which testifies to a wide variety of functional possibilities and areas of application. Formula isobteni A functional counter containing N bits, each of which is made on a 1K flip-flop, the synchronization input and the installation input zero of which are connected respectively to the clock bus and the installation zero bus, the first element I, the first input of which is connected to the direct output M1 second trigger, SECOND 6 input - with K-inputs of 1K-flip-flops of the first, second and N-ro bits, and vkhokho- with K-inputs of 1K triggers from the third co of N-th bits, the second element And, the first input of which is connected to the direct output 1K second trigger, and the second input — with the first bus accounts, in each bit, except the first one, contains the OR element, the output of each of which is connected to the 1-input of a 1K-trigger of its bit, the first and second inputs of the OR element of each of the bits, except the last, are connected to the direct outputs of the 1K-trigger, respectively, the previous and next bits, the first input of the element OR N-ro bit is connected to direct output 1K-trigger (N-1) -ro discharge, characterized in that, in order to expand the functionality and scope by providing an additional third conversion mode, additionally contains the third and fourth elements And, the element ИШ1, the second and the third control mode of the recalculation mode, the output of the additional ICH element is connected to the first input of the IK-trigger of the first bit, and the inputs to the outputs of the second and third elements of And, the first input of the third element And is connected to the inverse output of the IK-trigger of N-ro yes and second the input is with the second control bus of the conversion mode, the first input of the fourth element I is connected to the inverse output of the 1K trigger of the first bit, the second input is connected with the third bus of the control of the conversion mode, and the output with the second input of the element OR W-trigger of the N-ro discharge . La. fiin-ei nr feUI F1№.1 w.-r, w-e Ga "d1 ".X; I--.I- reiJI.