SU886247A1 - Functional counter - Google Patents

Description

(54) FUNCTIONAL SHBTCHIK

Claims (2)

An invention of computer technology and can & be used as a counter, a frequency divider with a variable factor (as well as for obtaining coherent code sequences of pulses.) Johnson's ring counter, known from the synchronous shift register, is inverse the output of the last bit of which is connected to the information input of the first bit. When the counter is in operation, the retaster bits are filled and then zero 1. The disadvantage of the known device is It is impossible to perform cyclic filling with single to zero states of an arbitrary duration and in an arbitrary sequence of register bits. The closest technical solution to the proposed is a functional counter to, containing an N-bit shift register, three control busbars, two control buses, four I-NB element and single pulse shaper 2. A disadvantage of the known functional counter is the insufficient counting volume and low reliability due to the small itelnostyu pulse taken from the N-oro discharge register defined by the time srabatshani shaper single pulses, pulse transit time set via two AND-NO element and the time of establishing the last row and ASP register in the original state. In addition, the device is relatively difficult. The purpose of the invention is to increase the counting volume and increase the reliability of the device. The goal is achieved by the fact that in a functional counter containing an N-bit shift register, a control trigger, two control points, four dow-input AND-NES elements, the first control element is connected to the first input of the first N-element and , the second control bus is connected to the first input of the second NAND element and the control trigger input, the output of the first NAND element is connected to the first input of the third AND-NAND element, the second input of which is connected to the inverse output of the control trigger, and the output of the third element AND-NOT is connected to the S-inputs of the shift register bits, except for the last, the output of the second element AND-NOT is connected to the first input of the fourth AND-NOT element, the second input of which is connected to the direct output of the control trigger and the information input of the first the shift register bit, and the output of the fourth element is NOT connected to the R-inputs of the register bits, except for the last one, the synchronization inputs of the register bits are connected to the counter input, the direct output of the last bit of the shift register is connected to the second input of the first of the NAND element, the inverse output of the last bit of the shift register is connected to the second input of the first NAND element, the inverse output of the last bit of the shift register is connected to the second input of the second NAND element, and the S and R inputs of the last bit of the register the shears are connected respectively to the first and second control buses. The drawing shows a diagram of a functional counter. The device contains a trigger 1 control, elements AND-NOT 2-5, N-bit shift register, control bus 7 and 8, and bus 9 clock pulses, which is the input of the counter. The control bus 7 is connected to the S input of control trigger 1, to the R input of the last register bit and to the first input of the NAND element 3, the second input of which is connected to the inverse output of the last register bit. The control bus 8 is connected to the I-input of the control trigger 1, to the S input of the last register bit and to the first input of the NAND element 2, the second input of which is connected to the forward output of the last bit of the shift register. The forward output of trigger 1 of control is connected to the information input of the first bit of the shift register and to the first input of the NAND element 5, the second input of which is connected to the output of the NAND element 3 and the output to the B inputs of all the shift register bits, except last, bit. The inverse output of the trigger 1 of control is connected to the first input of the element AND-NO 4, the second input of which is connected to the output of the element AND-NOT 2 and the output to the S-inputs of all of the shift register bits except the last one. The synchronization inputs of bits 6 "1 - the shift register is connected to the bus 9 clock pulses (the input of the counter). The device works as follows. In the initial state (after connecting the power supply) high voltage levels are present on buses 7 and 8, and there are no counting pulses on bus 9. When a low-level current level is applied to bus 7, the forward output of control trigger 1 is set to a high voltage level, which allows the register bits to be filled with single states, and the forward output of the last register bit is set to zero. NAND elements 3 and 5 are triggered, and a short zero voltage level appears at the inputs of the bits 6: N of the shift register, which sets them to the zero state. After the arrival of the first counting pulse on the bus 9, the first bit of the shift register switches and a unit voltage level is established at its forward output. After the (N-l) -ro arrival of the counting pulse, bus 9 switches the 6 «N-1 shift register and a single level of voltage appears at its forward output. After the arrival of the Nth rotor pulse, the unit voltage level appears at the forward output of the discharge of the 6-N shift register, and at its inverse output appears the zero level of voltage that is input to the AND-NOT element. 3 causes the appearance at its output of a single voltage level, which enters the input element AND-NOT 5. Since at the other input of the AND-HE element 5 there is a uniform voltage level from the direct output of control trigger 1, then from the output of the AND element -NOT 5, the zero voltage level is fed to the inputs of the bits — the 6-N shift register, sets them back to their original state, in which zero direct voltage levels are present at their direct outputs. Since the information input of the last digit of the 6-N shift register is set to zero voltage, after the arrival of the next counting pulse on bus 9, the last bit of the register also switches to the initial state, in which the zero output is present on its forward output voltage, and in the inverse output - a single voltage level, which enters the input element AND-NOT 3. Because at the other input element AND-PE 3 there is also a single voltage level from the control bus 7, then at the output element I-NO 3 establishes a zero voltage level, which causes the appearance at the output of an I-HE element 5 of a unit voltage level, thereby allowing the shift register bits to be filled with unit states. This cycle of filling with single states is repeated when there are counting pulses on the bus 9. Similarly, the functional counter operates when filling with zero states. In this case, after the application of the control pulse over the bus 8, the trigger 1 of the control | It is cast into a state in which a zero voltage level is present on its direct output, and a discharge is a 6N register in a state, in which unit voltage levels are present on their direct outputs. After the arrival of the counting pulses, the next 9 bits of the 6 "1 - 6-N register in turn are set to zero states, at which zero direct voltage levels are set at their direct outputs. When the last digit of the 6 "N register is established in the zero state, from its direct output, the zero voltage level is fed to the input of the AND-HE element 2, the output of which is the unit voltage level that goes to the input of the AND-element NOT 4. Since at the other input of the element AND-HE 4 there is a single voltage level from the inverse output of the control trigger 1, then at the output of the element AND-HE 4 there appears a zero voltage level that acts on the inputs of the bits - 6N-l shift register, sets them to outcome th state in KQTOpoM on straight outputs bits 6-1 are set unit na1f voltage levels. When the next counting impulse arrives on bus 9, the last bit of the 6-N register is also set to the initial unit state. In this case, a single voltage level appears at the output of the NAND 4 element, which allows the discharge of the 6N shift register to fill the zero states. Such a zero-state cycle is repeated in the presence of counting pulses on the bus 9. By operating on Shiam 7 and 8 in an arbitrary sequence, one can obtain the corresponding fill with one-time or zero states of the shift register bits. The construction of a functional counter according to the proposed scheme allows an increase in the counting volume and an increase in the reliability of the functional counter. The counting volume is increased by obtaining from the last bit of the counter a signal with a thickness equal to the clock period. In the known device, the duration of the signal from the last digit of the counter is determined by the response time of the single pulse generator, the two IS-NOT elements and the trt ger of the last digit of the register, so it is very small and unstable, which makes it impossible to use the signal from the last digit of the counter. The formula invented is also a Functional Counter, containing an N-bit shift register, a control trigger, control twins, four AND-NOT elements, the first control bus connected to the first input of the first AND-NAND element and the control trigger input, the second the control bus is connected to the first input of the second NAND element and the control trigger input, the output of the first NAND element is connected to the first input of the third NAND element, the second input of which is connected to the inverse output of the control trigger, and the third output I-NOT is connected to the S-inputs of the shift register bits, except for the last, the output of the second AND-NO element is connected to the first input of the fourth K-NE element, the second input of which is connected to the direct output of the control trigger and the information input of the first register bit the shift, and the output of the fourth element is NOT connected to the R inputs of the register bits, except the last one, the synchronization inputs of the register bits are coherent with the counter input, characterized in that, in order to increase the counting volume and increase the reliability of the device, direct output The last bit of the shift register is connected to the second input of the first NAND element, the inverse output of the last bit of the shift register is connected to the second input of the second NAND element, and the S and R-BXOs of the last bit shift are connected respectively to the first and second. management Sources of information taken into account prn examination 1.Gutnikov V.S. Integrated electronics in measuring devices. L., Energie, 1974, p.b5, fig. 32. 2. USSR author's certificate number 680177, cl. H 03 K 23/02, 1979.