SU600716A1 - Pulse recurrence frequency -to- voltage converter - Google Patents

Description

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The invention relates to electronic devices used in computing, automation, and telemechanics.

A known frequency converter is followed by pulses to voltage, a clock generator, a pulse shaper, whose duration is a multiple of the period of the clock generator, and a smoothing filter 1. The disadvantage of such a converter is a significant error arising during the conversion of high frequencies.

The closest to the technical essence of the invention is a pulse frequency to voltage converter comprising a generator of such pulses, a synchronizer, a counter and a smoothing filter 2. The first synchronizer input is connected to the first generator output, the second input of which is connected to the input terminal converter The disadvantage of this instructor is complexity.

The aim of the invention is to simplify the device. This goal is achieved by introducing a device for frequency subtraction into the converter, the first input of which is connected to the second output of the clock generator, and the output to the first input of the counter, and the commutator whose inputs are connected to the outputs of the synchronizer and the counter, and the outputs to the second inputs of the device for subtracting frequencies and the counter, the input of the smoothing filter and the keys to the output of the counter.

FIG. 1 shows the fuction electric circuit of the proposed converter; in fig. 2 - timing diagrams that show the operation of the converter.

The driver contains a generator 1

pulses, a synchronizer 2, a commutator 3, a counter 4, a device 5 for subtracting frequencies and a smoothing filter 6.

The first output of the synchronizer 2 is connected to the first output of the generator 1, the second

the input of which is connected to the input terminal 7 of the converter. The inputs of the device, 5 are connected to the second output of the generator 1 and the "output of the switch 3. The inputs of the switch 3 are connected to the outputs of the synchronizer 2 and

counter 4. The inputs of counter 4 connect with the outputs of switch 3 and device 5, and the output with input of the smoothing filter 6. Synchronizer 2 is a logic circuit with memory, and device 5 is

memory prohibition scheme: when a pulse arrives at one input, the next one will pass to the output; the pulse arrives at the second input. Switch 3 is a device that switches the input signal to one out of two outputs.

depending on the signal c. applied to the control input.

C (The output of the 1 clock pulse generator removes the pulse sequences Fi (Fig. 2, a) and FZ (Fig. 2, b) with the same pulse repetition rate F, shifted relative to each other in iBipeMewn in order to prevent their coincidence. On the back. The valuable terminal 7 is supplied by the pulses of the converted frequency fx (Fig. 2, c), which are correctly remembered at the memory of the synchronizer 2 and synchronized with the clock frequency impulses are inserted into the switch 3 (Fig. 2, d). Let senior counter size 4. is in STATUS ", with: From the counter input

4, a positive and potential + t / o (Fig. 2, g) is output to the control input of switch 3. This information allows the passage of pulses from the output of these axes, attorney 2 to the input} of device 5 for subtraction of frequencies and prohibits their passage and the second counter input 4. In this mode, the counter is filled 4 times the partial FI - fx, taken from the output of the device

5 (Fig. 2, d) and arriving at the first counting input of the counter 4, continuing until; until; At the time ti, the most significant bit is set to the state "O", i.e. the counter overflow occurs. At the same time, at the output of the counter 4, a negative potential Ug (fit. 2, g), which is fed to the control B1 input of the switch 3, is fed / injected, as a result of which impulses from the synchronizer 2 output to the device 5 are prohibited and the second counting input of the counter 4 (Fig. 2, s). In this mode, the counter is filled with the frequency FI at the first counting input AND with the frequency f at the second counting 1 INPUT, i.e. the counter 4 is filled with the sum of the frequency until the high-order bit of the counter 4 is set to "1 V time / a (Fig. 2, g) .. At this moment, the positive potential of + t / o is again set at the output of counter 4 and it is filled with the difference frequency

F, -fx.

Thus, the output of the counter 4 is periodically set to the potentials

+ t / o and -UD, equal in absolute B: to the value. The average value of the voltage generated by the smoothing filter 6 is equal to

zg z up f

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where k is the transfer coefficient of the smoothing filter. The range of Pr | convertible frequencies f is determined by the following conditions; the maximum value of the frequency to be converted / xmax should not exceed the value of FI, i.e. fxmnx F to eliminate information loss, (the minimum value of frequency /.vmiu is determined

the parameters of the smoothing filter 6 and additional} is the feasible coefficient of zero voltages output voltage.

The proposed transducer has a higher nastro than the known circuit, eo.hran at the same time, all its positive properties :.

F o rm} l and inventions

A pulse frequency to voltage converter, containing a clock pulse generator, to the first output of which the first input of the synchronizer is switched on and the second input of which is connected to the input

a terminal block, a counter smoothing filter, which is due to the fact that, for the purpose of simplification, a frequency subtractor, the first

the input of which is connected to the second output}

the clock generator, and the output to the first input of the counter, and the switch, the inputs of which are connected to the output of the synchronizer and the counter, and the outputs to the second inputs of the device for frequency subtraction and the counter,

moreover, the input of the smoothing filter is connected to the BbiiXOTy account.

Sources of information taken into account in the examination

1. US Patent No. 3591858, cl. 307-255, 1967.

2. Authors certificate of the USSR LL 432674, cl. H OZK 13/12, 1972.

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