SU435524A1 - POSSIBLE-PERFORMANCE DEVICE - Google Patents

Description

one

The device relates to computing.

A multiplying-divider device is known that contains the first counter, the counting input of which is connected to the first input device and the outputs, respectively, with the first inputs of the AND circuits, the second inputs of which are combined, and the outputs connected to the corresponding inputs of the second counter, and the trigger, single output which is connected to the first input of the “I” circuit, the second input of which is connected to the second bus of the device, and the output to the counting input of the third counter.

However, in such a device, the integration is performed in two cycles. This reduces the speed of the device.

The purpose of the invention is to increase the speed of the device.

This is achieved by connecting the third input bus of the device to the control input of the first counter, to the combined second inputs of the AND schemes and to the single trigger input, the zero input of which is connected to the output of the second counter, the counting input of which is connected to the output of the additional AND circuit. , the first input of which is connected to the fourth input bus of the device,

and the second input - with a single trigger output.

The drawing shows a diagram of the device.

The device contains counters 1-3, circuit "And 4-b, trigger 7. At the inputs 8-11 receive input values.

The device works as follows. Input 8 (first input bus) is fed a signal with frequency / i to input 9 (second input bus) - a signal with frequency / 2, input 10 (third input bus) - a signal with duration TI and input 11 (fourth input

bus) - signal with frequency / s -. At the end

Tz

the TI interval, the inverse code of the number that is generated in counter 1 is transferred to counter 2, counter 1 is reset to position "O, and trigger 7 is set to position" 1. Trigger 7 opens the schemes "And 5," And 6. Now the signals pass to all counters. When 2 NI pulses arrive in the counter, the latter overflows, and the sigpal returns a trigger 7 to “O.” Circuits "And 5 and" And 6 are closed.

Scheme "And 5 is open over time

, -.AGT - ftlL

2 - I- 3 -,

thirty

/ 3

During this time, in the counter 3, the code defined by the expression:

l / -4

f / 1-L

/ Vj / a -

/ 3

/ 3

Integration in counters 1 and 2 is performed simultaneously, therefore, for normal operation of the device, it is necessary, where n is the NUMBER of bits in the counters. Since the TI intervals can follow continuously, then the input 10 can be fed

signal with frequency fo -. Then the code in the counting 1

ke 3 will be defined by the expression:

LL

L- / o

Subject invention

A multiplier-effect device containing the first counter, the counting input of which is connected to the first input bus of the device, and the outputs - ebt respectively with the first inputs of the “And” circuits, the second inputs of which are combined, and the output connected to the corresponding inputs of the second counter, and a trigger whose unit OUTPUT "The first input of the circuit" And, the second input of which is connected to the second input bus of the device, and the output - to the counting input of the third counter, characterized in that, in order to increase speed, a third input voltage connected to the control input of the first counter, with the combined second inputs of the AND circuits, and with the single input of the trigger, the zero input of which is connected to the output of the second counter, the counting input of which is connected to the VYoDvM of the additional output I, and the first input of which is connected to the fourth the input bus of the device, and the second input - with a single trigger output.

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with/

LN

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