SU677084A1 - Pulse delay device - Google Patents

Description

This is the output to the other input of the NO element, the first input is to the second input of the first Ceptill and through the serially connected differentiating circuit and the delay element to the zero input of the trigger, and the second input to the single output of the trigger, an additional delay element, a valve and a trigger are introduced, with This output of the generator of counting pulses is connected via an additional delay element to the first input of an additional valve connected by a second input to the output of an additional trigger, and the output to a single input of the main trigger and to the single input of the additional trigger, the zero input of which is connected to the output of the decoder zero.

The drawing shows the functional diagram of the device.

The device contains the first 1 and second

2 fans, element NO 3, generator 4 counting pulses, decoder 5 zero, reversible counter 6, trigger 7, differentiating circuit 8, delay element 9, element 10, additional delay element 11, valve 12 and trigger 13.

The device works as follows.

The rectangular impulse that needs to be delayed goes to the first input of element 10. At the second input of element 10, a zero potential acts at this time from the single output of trigger 7, which is at the moment of arrival of the delayed pulse in the state "O. This is at the control input of the item NO.

3 there is no prohibitive voltage, and the pulses of the generator 4 arrive at

inputs of valves 1 and 2.

At the same time, the rectangular impulse that needs to be delayed is fed to the control input of the valve 1, with which the reversible counter 9 is filled with the counting pulses of the generator 4. Thus, the delayed signal is converted into pulses whose number is proportional to its duration. These pulses are fed to the summing input of the reversible counter 6.

Also, a simultaneously delayed pulse is applied to the differentiation circuit 8, where it is converted into two short pulses. The pulse corresponding to the front of the original signal is delayed by the delay element 9, after which it arrives at the zero input of the trigger 7. When the delayed pulse arrives at the control input of the valve 2, the inhibiting voltage from the output of the trigger 7 acts. The output pulse of the delay element 9 flips the trigger 7 into a state of "1", and from that moment on, a control voltage appears at the control input of the valve 2.

If the delay time of a rectangular pulse is longer than its duration, then while trigger 7 remains in state "1, the counting pulses of generator 4 pass through gate 2 to the subtracting input of the reversing counter 6. After the number of pulses supplied to the subtracting input of the counter 6, will be equal to the previously entered through the summing input,

the counter 6 is completely cleaned and a pulse appears at the output of the decoder zero 5. This pulse sets the trigger 13 and opens the valve 12. The pulse from the output of the generator 4, which, after passing the element NO 3 and the valve 2, clears the counter 6, simultaneously arrives at the input of the element 11 delay. This pulse from the output of the delay element 11, calculated on the half-period of the counting pulses

generator 4, passes through the open valve 12 and returns the triggers 7 and 13 to the initial state "O.

If the delay time of a rectangular pulse is shorter than its duration, then after trigger 7 is transferred to the state "1", high potentials act on both inputs of the And 10 element. In this case, a forbidden voltage appears at the control input of the element NO 3, and

the counting input and the subtracting input of the reversing counter 6 do not receive the counting pulses of generator 4. At the time of the end, a delayed pulse at the control input is input to the device

element NO 3, the inhibiting voltage ceases to act, and the counting pulses of the generator 4 arrive at the signal inputs of gates 1 and 2. But the enabling voltage is present only at the control input of the gate 2, therefore the counting pulses go to the subtracting input of counter 4. After the number of pulses applied to the subtracting input of the counter will be equal to the previously entered

through the summing input, the counter is completely cleared, and a pulse appears at the output of the zero decoder. This pulse sets the trigger 13 to the state "1 and opens the valve 12. The counting pulse, which zeroed the contents of the counter, is delayed in the AND delay element, and then, after passing through the open valve 12, returns the triggers 7 and 13 to the initial state O.

As a result of a double flip of the trigger 7, a rectangular pulse delayed relative to the original signal is formed at its output. At the same time in the device due to the additional delay

the trailing edge of the output pulse for a half-period of the following counting pulses eliminates the systematic component of the error that occurs when converting a digital code into a delayed pulse duration, therefore the total

the conversion error is equal to the rms.

Claims (2)

1. USSR author's certificate number 529552, cl. N OZK 5/13, 09.06.75. 2. USSR author's certificate number 558389, cl. H 03 K 5/13, 04.22.75.