SU660220A2 - Analogue-digital device for delay of square-wave pulses - Google Patents

Description

one

The invention relates to a pulse technique and can be used in measuring and computing technology.

The analog-digital device for delaying rectangular pulses is known from aut. St. No. 530441 containing a counting pulse generator, three valves, a switch, two triggers, an OR element, a pulse edge delay unit, a differentiating circuit, two pulse counters, and a matching element 1.

However, this device has insufficient noise immunity, because during the pulse delay time new impulses may arrive at the device input, which would entail a corresponding distortion of the delayed impulse duration at the device output compared to the input pulse duration.

The purpose of the invention is to increase the noise immunity of the device.

To do this, an analog-to-digital device for delaying rectangular pulses containing a counting pulse generator, three valves, a switch, two triggers, an OR element, a pulse front delay block, a differentiating circuit, two pulse counters, and a code matching element, introduced an additional gate whose input connected to the source of delayed pulses, and the output to the control input of the first valve and to the input of the differentiating circuit, an additional trigger, the output of which is connected to the control input of the additional vein yl, and a single input - to the input circuit of the first reset pulse counter, and an inverter having an input connected to the output of the differentiating circuit, and an output - to zero

additional trigger input.

The drawing shows a block diagram of the proposed device.

The device contains a generator 1 counting pulses, valves 2-5, counters 6, 7

pulses the element 8 coincidence codes, differentiating circuit 9, block 10 of the pulse-front delay, element OR 11, triggers 12-14, inverter 15 and switch 16, input 17 of delayed pulses

and the output 18 of the delayed pulse. The input 17 through the valve 5 is connected to the control input of the valve 2 and to the input of the differentiating circuit 9, the output connected by the input g of the unit 10 and through the inverter 15 - sleep

the left input of the trigger 14, a single output of which is connected to the control input of the valve 5. The control input of the valve 3 is connected to the zero output of the trigger 12. The output of the generator 1 is connected through the valve 2 to the input of the counter 6 and through

valve 3 - to the input of the counter 7, the outputs of the block 10 - to the control inputs of the switch 16 and through the element OR AND to the zero input of the trigger 12, the last output of the block 10 is also connected to the zero input of the trigger 13. The outputs of the counters 6 and 7 through the element 8 are connected to the signal input of the valve 4, the reset input of the counter 7 and the single input of the trigger 12. The zero output of the trigger 13 is connected to the control input of the valve 4, the output of which is connected to the reset input of the counter 6 and to the single inputs of the trigger 13 and 14. Single output of the trigger 13 12 connected to the output 18, is connected to the signal input of the switch 16. The switch 16 outputs serve as outputs of the device under conditions rendition multichannel signals.

The device works as follows.

A rectangular impulse from input 17 is fed through valve 5, the control input of which has the "allowable voltage of a single output of the trigger 14, to the control input of the valve 2, to the signal input of which the counting pulses of the generator 1 are fed.

Thus, the delayed signal is converted into pulses, the number of which is proportional to its duration. These pulses are fed to the input of the counter 6.

A parallel delayed pulse is applied to differentiating circuit 9, where it is converted into two short pulses. The impulse corresponding to the leading edge of the original signal is delayed in block 10 at time 7i, after which the OR element 11 arrives at the zero input of the trigger 12. The impulse corresponding to the trailing edge of the original signal through the inverter 15 falls into the zero input of the trigger 14 and transfers it to state "O. In this case, a "prohibitive voltage" is created at the control input of the valve 5. While trigger 14 is in this state, new source pulses cannot pass through valve 5.

Prior to operation, triggers 12 and 13 are in the zero state. In this case, at the inputs of valves 3 and 4, "prohibiting voltages are in effect. The output pulse, taken from the first output of block 10, flips trigger 12 to the state "1. From this point on, the input voltage of the valve 3 appears. While trigger 12 is in state "1, the counting pulses of generator 1 pass through gate 3 at the input of counter 7. After the number of these pulses is equal to the number entered earlier in counter 6, the pulse 8 appears at the output of element 8, which sets trigger 12 to its original position and is fed to the reset input of the counter 7.

As a result of a double flip of the trigger 12, a rectangular pulse is generated at its output, delayed by time Ji with respect to the original signal. This pulse, having the same duration as the initial pulse, is output to the output 18 of the device. At interval T, a pulse arises at the second output of block 10. It enters through the element OR 11 at the zero input of trigger 12 and transfers it to the state "1. From this moment, an allow voltage appears at the inlet of the valve 3. While trigger 12 is in state "1, the counting pulses of generator 1

pass through the valve 3 to the input of the counter 7. After the number of these pulses is equal to the number of pulses recorded in the counter 6, the output of the element 8 appears a pulse that sets the trigger 12 to its original position and enters the input of the counter 7. As a result of a double flip of the trigger 12, a rectangular pulse is generated at its output, delayed by the time TZ but relative to the original signal.

Further, the device works in a similar way when it appears on K-s. the output of block 10 of a pulse corresponding to a delayed edge of the original signal is formed by a rectangular pulse delayed by time T. The impulse taken from the last output of block 10, i.e., from the output corresponding to the maximum delay of 7 ", goes both to the zero input of the trigger 12, so

and to the zero input of the trigger 13, transferring them to the state "1. At the same time, at the inlet of the valve 4, a “permissive effect” acts. Now the pulse, which is at the end of the output of element 8, at the moment of termination

The last delayed imiuls will pass through the valve 4 to the reset input of the counter 6 and clean it, and also go to the single inputs of the flip-flops 13, 14 and set them to the initial state. At the same time, the "enabling voltage" appears at the control input of the valve 5, and the device is again ready to receive and delay the next pulse. Delayed rectangular pulses

served from the output of the trigger 12 to the signal input of the switch 16, which is controlled by the inputs of the pulses taken from the outputs of the block 10. When a pulse appears at the i-M output of the block 10, a delayed rectangular pulse appears at the i-M output of the switch 16.

Claims (1)

Invention Formula Analog-to-digital device for delaying rectangular pulses according to ed. St. No. 530441, characterized in that, in order to increase the noise immunity of the device, additional a valve whose input is connected to a source of delayed pulses, and an output to the control input of the first valve and to the input of the differentiating circuit, an additional trigger whose output is connected to the control input of the additional valve, and a single input to the input of the reset circuit of the first pulse counter, and an inverter, whose input is connected to the output of the differentiating circuit, and the output to the zero input of an additional trigger. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 530441, cl. N OZN 5/13, 1975. III 0000 J